"Hongye Huang,Hanli Liu,Zheng Sun,Dingxin Xu,�õ’J �WŠî,”’�ª “ÄŽj,‰ª“c Œ’ˆê","A 2.4GHz Low-Power Subsampling/Sampling-Mixed Fractional-N All-Digital PLL","“dŽq�î•ñ’Ê�MŠw‰ï ƒ\ƒTƒCƒGƒeƒB‘å‰ï",,,,,,2019,Sept.
"Dingxin Xu,Zheng Sun,Hongye Huang,�õ’J �WŠî,”’�ª “ÄŽj,‰ª“c Œ’ˆê","A Time-Amplifier Gain Calibration Technique for ADPLL","“dŽq�î•ñ’Ê�MŠw‰ï ƒ\ƒTƒCƒGƒeƒB‘å‰ï",,,,,,2019,Sept.
"Zheng Sun,Dingxin Xu,Hongye Huang,�õ’J �WŠî,”’�ª “ÄŽj,‰ª“c Œ’ˆê","A 78fs RMS Jitter Injection-Locked Clock Multiplier Using Transformer-Based Ultra-Low-Power VCO","“dŽq�î•ñ’Ê�MŠw‰ï ƒ\ƒTƒCƒGƒeƒB‘å‰ï",,,,,,2019,Sept.
"Zheng Sun,Hanli Liu,Dingxin Xu,Hongye Huang,Bangan Liu,Zheng Li,Jian Pang,Teruki Someya,Atsushi Shirane,Kenichi Okada","A 78fs RMS Jitter Injection-Locked Clock Multiplier Using Transformer-Based Ultra-Low-Power VCO","IEEE European Solid-State Circuits Conference (ESSCIRC)",,,,,,2019,Sept.
"Dingxin Xu,Hanli Liu,Zheng Sun,Hongye Huang,Wei Deng,Teerachot Siriburanon,Jian Pang,Yun Wang,Rui Wu,�õ’J �WŠî,”’�ª “ÄŽj,‰ª“c Œ’ˆê","A 265-?W Fractional-N Digital PLL with Switching Subsampling/Sampling Feedback","“dŽq�î•ñ’Ê�MŠw‰ï LSI‚ƃVƒXƒeƒ€‚̃��[ƒNƒVƒ‡ƒbƒv",,,,,,2019,May