論文

• Koh Yamanaga, Shuhei Amakawa, Kazuya Masu, Takashi Sato. A Universal Equivalent Circuit Model for Ceramic Capacitors, IEICE Transactions on Fundamentals of Electronics, IEICE Transactions on Fundamentals of Electronics, IEICE Transactions on Fundamentals of Electronics, Vol. E93-C, No. 3, pp. 347-354, Mar. 2010.
• Takumi Uezono, Kazuya Masu, Takashi Sato. A Time-Slicing Ring Oscillator for Capturing Time-Dependent Delay Degradation and Power Supply Voltage Fluctuation, IEICE Transactions on Fundamentals of Electronics, IEICE Transactions on Fundamentals of Electronics, vol. E93-C, no. 3, pp. 324–331, Mar. 2010.
• Takashi Sato, Hiroyuki Ueyama, Noriaki Nakayama, Kazuya Masu. Accurate array-based measurement for subthreshold-current of MOS, IEEE Journal of Solid-State Circuits, IEEE Journal of Solid-State Circuits, Vol. 44, No. 11, pp. 2977-2986, Nov. 2009.

国際会議発表 (査読有り)

• Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato. Scan Based Process Parameter Estimation Through Path-Delay Inequalities, IEEE International Symposium on Circuits and Systems (ISCAS 2010), IEEE International Symposium on Circuits and Systems (ISCAS 2010), IEEE International Symposium on Circuits and Systems (ISCAS 2010), June 2010.  公式リンク  
  
• Takashi Sato, Takumi Uezono, Noriaki Nakayama, Kazuya Masu. Decomposition of Drain-Current Variation Into Gain-Factor and Threshold Voltage Variations, IEEE International Symposium on Circuits and Systems (ISCAS 2010), IEEE International Symposium on Circuits and Systems (ISCAS 2010), IEEE International Symposium on Circuits and Systems (ISCAS 2010), May 2010.
• Takanori Date, Shiho Hagiwara, Kazuya Masu, Takashi Sato. Robust importance sampling for efficient SRAM yield analysis, International Symposium on Quality Electronic Design (ISQED), International Symposium on Quality Electronic Design (ISQED), International Symposium on Quality Electronic Design (ISQED), pp. 15-21, Mar. 2010.
• Shiho Hagiwara, Koh Yamanaga, Ryo Takahashi, Kazuya Masu, Takashi Sato. Linear Time Calculation of State-Dependent Power Distribution Network Capacitance., International Symposium on Quality Electronic Design (ISQED), International Symposium on Quality Electronic Design (ISQED), International Symposium on Quality Electronic Design (ISQED), pp. 75-80, Mar. 2010.
• Tomoyuki Takahashi, Takumi Uezono, Michihiro Shintani, Kazuya Masu, Takashi Sato. On-die parameter extraction from path-delay measurements, 2009 IEEE Asian Solid-State Circuits Conference, 2009 IEEE Asian Solid-State Circuits Conference, IEEE Asian Solid-State Circuits Conference, pp. 101 - 104, Nov. 2009.
• Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Hiroyuki Ueyama, Takashi Sato, Kasumi Hatayama, Takashi Aikyo, Kazuya Masu. An Adaptive Test for Parametric Faults Based on Statistical Timing Information, IEEE Asian Test Symposium, IEEE Asian Test Symposium, IEEE Asian Test Symposium, pp. 151-156, Nov. 2009.

国内会議発表 (査読有り)

• 伊達貴徳, 萩原 汐, 益 一哉, 佐藤高史. 超球の一部を用いた歩留り推定における不良領域の効率的探索手法, VLSI設計技術研究会，電子情報通信学会技術研究報告, VLSI設計技術研究会，電子情報通信学会技術研究報告, VLSI設計技術研究会，電子情報通信学会技術研究報告, pp. 37-42, Mar. 2010.

国内会議発表 (査読なし・不明)

• 高橋知之, 上薗巧, 越智裕之, 益一哉, 佐藤高史. パス遅延測定によるチップ特性の推定手法, DAシンポジウム, DAシンポジウム, DAシンポジウム, pp. 133-138, Aug. 2009.

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