@article{CTT100678329,
  author = {Ittetsu  Taniguchi and Junya Kaida and Takuji Hieda and Yuko Hara-Azumi and Hiroyuki  Tomiyama},
  title = {Static Mapping with Dynamic Switching of Multiple Data-Parallel Applications on Embedded Many-core SoCs},
  journal = {IEICE Transactions on Information and Systems},
  year = 2014,
}

@article{CTT100679132,
  author = {Yuko Hara-Azumi and Toshinobu Matsuba and Hiroyuki Tomiyama and Shinya Honda and Hiroaki Takada},
  title = {Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs},
  journal = {IPSJ Transactions on System LSI Design Methodology},
  year = 2014,
}

@article{CTT100679134,
  author = {Junya Kaida and Yuko Hara-Azumi and Takuji Hieda and Ittetsu Taniguchi and Hiroyuki Tomiyama and Koji Inoue},
  title = {Static Mapping of Multiple Data-Parallel Applications on Embedded Many-core SoCs},
  journal = {IEICE Transactions on Information and Systems},
  year = 2013,
}

@article{CTT100679135,
  author = {Yuko Hara-Azumi and Toshinobu Matsuba and Hiroyuki Tomiyama and Shinya Honda and Hiroaki Takada},
  title = {Quantitative Evaluation of Resource Sharing in High-Level Synthesis Using Realistic Benchmarks},
  journal = {IPSJ Transactions on System LSI Design Methodology},
  year = 2013,
}

@article{CTT100679137,
  author = {Yuko Hara and Hiroyuki Tomiyama and Shinya Honda and Hiroaki Takada},
  title = {Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism},
  journal = {IEICE Transactions on Fundamentals of Electronics,Communications and Computer Sciences},
  year = 2010,
}

@article{CTT100679138,
  author = {Yuko Hara and Hiroyuki Tomiyama and Shinya Honda and Hiroaki Takada},
  title = {Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis},
  journal = {Journal of Information Processing},
  year = 2009,
}

@article{CTT100679139,
  author = {Seiya Shibata and Shinya Honda and Yuko Hara and Hiroyuki Tomiyama and Hiroaki Takada},
  title = {Embedded System Covalidation with RTOS Model and FPGA},
  journal = {IPSJ Transactions on System LSI Design Methodology},
  year = 2008,
}

@article{CTT100679140,
  author = {Yuko Hara and Hiroyuki Tomiyama and Shinya Honda and Hiroaki Takada and Katsuya Ishii},
  title = {Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis},
  journal = {IEICE Transactions on Fundamentals of Electronics,Communications and Computer Sciences},
  year = 2007,
}

@article{CTT100679141,
  author = {Yuko Hara and Hiroyuki Tomiyama and Shinya Honda and Hiroaki Takada},
  title = {Function Call Optimization for Efficient Behavioral Synthesis},
  journal = {IEICE Transactions on Fundamentals of Electronics,Communications and Computer Sciences},
  year = 2007,
}

@inproceedings{CTT100679142,
  author = {Stefan Hadjis and Andrew Canis and Ryoya Sobue and Yuko Hara-Azumi and Hiroyuki Tomiyama and Jason Anderson},
  title = {Profiling-Driven Multi-Cycling in FPGA High-Level Synthesis},
  booktitle = {},
  year = 2015,
}

@inproceedings{CTT100679143,
  author = {Yuko Hara-Azumi and Toshihiko Kamata and Ittetsu Taniguchi and Hiroyuki Tomiyama},
  title = {Yield-Aware Allocation and Binding of Partially-Programmable Functional Units},
  booktitle = {},
  year = 2014,
}

@inproceedings{CTT100679146,
  author = {Ryoya Sobue and Yuko Hara-Azumi and Hiroyuki Tomiyama},
  title = {Partial Controller Retiming in High-Level Synthesis},
  booktitle = {},
  year = 2013,
}

@inproceedings{CTT100679148,
  author = {Yuko Hara-Azumi and Hiroyuki Tomiyama},
  title = {Cost-Efficient Scheduling in High-Level Synthesis for Soft-Error Vulnerability Mitigation},
  booktitle = {},
  year = 2013,
}