論文

• Ittetsu Taniguchi, Junya Kaida, Takuji Hieda, Yuko Hara-Azumi, Hiroyuki Tomiyama. Static Mapping with Dynamic Switching of Multiple Data-Parallel Applications on Embedded Many-core SoCs, IEICE Transactions on Information and Systems, vol. E97-D, no. 11, pp. 2827-2834, Nov. 2014.
• Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada. Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs, IPSJ Transactions on System LSI Design Methodology, vol. 7, pp. 37-45, Feb. 2014.
• Junya Kaida, Yuko Hara-Azumi, Takuji Hieda, Ittetsu Taniguchi, Hiroyuki Tomiyama, Koji Inoue. Static Mapping of Multiple Data-Parallel Applications on Embedded Many-core SoCs, IEICE Transactions on Information and Systems, vol. E96-D, no. 10, pp. 2268-2271, Oct. 2013.
• Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada. Quantitative Evaluation of Resource Sharing in High-Level Synthesis Using Realistic Benchmarks, IPSJ Transactions on System LSI Design Methodology, vol. 6, pp. 122-126, Aug. 2013.
• Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada. Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism, IEICE Transactions on Fundamentals of Electronics,Communications and Computer Sciences, vol. E93-A, no. 2, pp. 488-499, Feb. 2010.
• Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada. Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis, Journal of Information Processing, vol. 17, pp. 242-254, Oct. 2009.
• Seiya Shibata, Shinya Honda, Yuko Hara, Hiroyuki Tomiyama, Hiroaki Takada. Embedded System Covalidation with RTOS Model and FPGA, IPSJ Transactions on System LSI Design Methodology, vol. 1, pp. 126-130, Aug. 2008.
• Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii. Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis, IEICE Transactions on Fundamentals of Electronics,Communications and Computer Sciences, vol. E90-A, no. 12, pp. 2853-2862, Dec. 2007.
• Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada. Function Call Optimization for Efficient Behavioral Synthesis, IEICE Transactions on Fundamentals of Electronics,Communications and Computer Sciences, vol. E90-A, no. 9, pp. 2032-2036, Sept. 2007.

国際会議発表 (査読有り)

• Stefan Hadjis, Andrew Canis, Ryoya Sobue, Yuko Hara-Azumi, Hiroyuki Tomiyama, Jason Anderson. Profiling-Driven Multi-Cycling in FPGA High-Level Synthesis, Design, Automation & Test in Europe, Mar. 2015.
• Ryoya Sobue, Yuko Hara-Azumi, Hiroyuki Tomiyama. Partial Controller Retiming in High-Level Synthesis, Electronic System Level Synthesis Conference, pp. 10-15, May 2013.
• Yuko Hara-Azumi, Hiroyuki Tomiyama. Cost-Efficient Scheduling in High-Level Synthesis for Soft-Error Vulnerability Mitigation, International Symposium on Quality Electronic Design, pp. 518-523, Mar. 2013.

国際会議発表 (査読なし・不明)

• Yuko Hara-Azumi, Toshihiko Kamata, Ittetsu Taniguchi, Hiroyuki Tomiyama. Yield-Aware Allocation and Binding of Partially-Programmable Functional Units, International Technical Conference on Circuits/Systems, Computers and Communications, pp. 729-732, July 2014.

[ BibTeX 形式で保存 ]    [ 論文・著書をCSV形式で保存 ]    [ 特許をCSV形式で保存 ]