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SunZheng 2019年 研究業績一覧 (14件 / 47件)
論文
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Hanli Liu,
Zheng Sun,
Hongye Huang,
Wei Deng,
Teerachot Siriburanon,
Jian Pang,
Yun Wang,
Rui Wu,
Teruki Someya,
Atsushi Shirane,
Kenichi Okada.
A 265-µW Fractional-N Digital PLL with Seamless Automatic Switching Sub-sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS,
IEEE Journal of Solid-State Circuits (JSSC),
Vol. 54,
No. 12,
pp. 3478-3492,
Dec. 2019.
国際会議発表 (査読有り)
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Zheng Sun,
Hanli Liu,
Dingxin Xu,
Hongye Huang,
Bangan Liu,
Zheng Li,
Jian Pang,
Teruki Someya,
Atsushi Shirane,
Kenichi Okada.
A 78fs RMS Jitter Injection-Locked Clock Multiplier Using Transformer-Based Ultra-Low-Power VCO,
IEEE European Solid-State Circuits Conference (ESSCIRC),
Sept. 2019.
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Jian Pang,
Zheng Li,
Ryo Kubozoe,
Xueting Luo,
Rui Wu,
Yun Wang,
Dongwon You,
Ashbir Aviat Fadila,
Rattanan Saengchan,
Takeshi Nakamura,
Joshua Alvin,
Daiki Matsumoto,
Tn Aravind,
Bangan Liu,
Hanli Liu,
Zheng Sun,
Hongye Huang,
Korkut Kaan Tokgoz,
Naoki Oshima,
Keiichi Motoi,
Shinichi Hori,
Kazuaki Kunihiro,
Tomoya Kaneko,
Atsushi Shirane,
Kenichi Okada.
A 28GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR,
IEEE International Solid-State Circuits Conference (ISSCC),
pp. 344-345,
Feb. 2019.
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Hanli Liu,
Zheng Sun,
Hongye Huang,
Wei Deng,
Teerachot Siriburanon,
Jian Pang,
Yun Wang,
Rui Wu,
Teruki Someya,
Atsushi Shirane,
Kenichi Okada.
A 265-µW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS,
IEEE International Solid-State Circuits Conference (ISSCC),
pp. 256-257,
Feb. 2019.
国内会議発表 (査読なし・不明)
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Hongye Huang,
Hanli Liu,
Zheng Sun,
Dingxin Xu,
染谷 晃基,
白根 篤史,
岡田 健一.
A 2.4GHz Low-Power Subsampling/Sampling-Mixed Fractional-N All-Digital PLL,
電子情報通信学会 ソサイエティ大会,
Sept. 2019.
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Zheng Sun,
Dingxin Xu,
Hongye Huang,
染谷 晃基,
白根 篤史,
岡田 健一.
A 78fs RMS Jitter Injection-Locked Clock Multiplier Using Transformer-Based Ultra-Low-Power VCO,
電子情報通信学会 ソサイエティ大会,
Sept. 2019.
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Dingxin Xu,
Zheng Sun,
Hongye Huang,
染谷 晃基,
白根 篤史,
岡田 健一.
A Time-Amplifier Gain Calibration Technique for ADPLL,
電子情報通信学会 ソサイエティ大会,
Sept. 2019.
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Dingxin Xu,
Hanli Liu,
Zheng Sun,
Hongye Huang,
Wei Deng,
Teerachot Siriburanon,
Jian Pang,
Yun Wang,
Rui Wu,
染谷 晃基,
白根 篤史,
岡田 健一.
A 265-µW Fractional-N Digital PLL with Switching Subsampling/Sampling Feedback,
電子情報通信学会 LSIとシステムのワークショップ,
May 2019.
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Zheng Sun,
Hanli Liu,
Dexian Tang,
Hongye Huang,
金子 徹,
Rui Wu,
Wei Deng,
染谷 晃基,
白根 篤史,
岡田 健一.
A T/R Switch Embedded BLE Transceiver with 2.6mW Harmonic-Suppressed Transmitter and 2.3mW Hybrid-Loop Receiver」,,
電子情報通信学会 LSIとシステムのワークショップ,
May 2019.
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Hongye Huang,
Hanli Liu,
Zheng Sun,
Teruki Someya,
Atsushi Shirane,
Kenichi Okada.
An Energy-Saving Digital-to-Time Converter for Ultra-Low-Power Digital PLLs,
電子情報通信学会 集積回路研究会,
Vol. ICD2018-116,
No. 507,
pp. 87-91,
Mar. 2019.
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Jian Pang,
Zheng Li,
窪添 諒,
Xueting Luo,
Rui Wu,
Yun Wang,
Dongwon You,
Ashbir Aviat Fadila,
Rattanan Saengchan,
中村 岳資,
Joshua Alvin,
松本 大輝,
THARAYILNAARAVIND,
Bangan Liu,
Junjun Qiu,
Hanli Liu,
Zheng Sun,
Hongye Huang,
白根 篤史,
岡田 健一.
双方向動作可能な5GNR二偏波MIMO対応28GHz帯CMOSフェーズドアレイ無線機,
電子情報通信学会 集積回路研究会,
Vol. ICD2018-106,
No. 507,
pp. 31-35,,
Mar. 2019.
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Pang Jian,
Zheng Li,
Ryo Kubozoe,
Xueting Luo,
Rui Wu,
Yun Wang,
Dongwon You,
Ashbir Aviat Fadila,
Rattanan Saengchan,
Takeshi Nakamura,
Joshua Alvin,
Daiki Matsumoto,
Tn Aravind,
Bangan Liu,
Hanli Liu,
Zheng Sun,
Hongye Huang,
Korkut Kaan Tokgoz,
大島 直樹,
元井 桂一,
堀 真一,
國弘 和明,
Tomoya Kaneko,
Atsushi Shirane,
Kenichi Okada.
A 28GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR,
IEEE SSCS Japan Chapter ISSCC報告会,
Mar. 2019.
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Zheng Sun,
Hanli Liu,
Dexian Tang,
Hongye Huang,
Tohru Kaneko,
Rui Wu,
Wei Deng,
Teruki Someya,
Atsushi Shirane,
Kenichi Okada.
A 0.85mm2 BLE Transceiver with Embedded T/R Switch, 2.6mW Fully-Passive Harmonic Suppressed Transmitter and 2.3mW Hybrid-Loop Receiver,
電子情報通信学会 集積回路研究会,
Vol. ICD2018-115,
No. 507,
pp. 81-85,
Mar. 2019.
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Hanli Liu,
Zheng Sun,
Hongye Huang,
Wei Deng,
Teerachot Siriburanon,
Pang Jian,
Yun Wang,
Rui Wu,
染谷 晃基,
Atsushi Shirane,
Kenichi Okada.
A 265-µW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS,
IEEE SSCS Japan Chapter ISSCC報告会,
Mar. 2019.
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