@inproceedings{CTT100772090,
  author = {Masayuki Shimoda and Shimpei Sato and Hiroki Nakahara},
  title = {All Binarized Convolutional Neural Network and Its implementation on an FPGA},
  booktitle = {},
  year = 2017,
}

@inproceedings{CTT100772089,
  author = {Hiroki Nakahara and Haruyoshi Yonekawa and Shimpei Sato},
  title = {An Object Detector based on Multiscale Sliding Window Search using a Fully Pipelined Binarized CNN on an FPGA},
  booktitle = {},
  year = 2017,
}

@inproceedings{CTT100772091,
  author = {Hiroki Nakahara and Tomoya Fujii and Shimpei Sato},
  title = {A Fully Connected Layer Elimination for a Binarized Convolutional Neural Network on an FPGA},
  booktitle = {},
  year = 2017,
}

@inproceedings{CTT100772092,
  author = {Hiroki Nakahara and Haruyoshi Yonekawa and Tomoya Fujii and Masayuki Shimoda and Shimpei Sato},
  title = {GUINNESS: A GUI based neural network synthesizer for an FPGA},
  booktitle = {},
  year = 2017,
}

@inproceedings{CTT100772093,
  author = {Kota Ando and Kodai Ueyoshi and Kazutoshi Hirose and Kentaro Orimo and Haruyoshi Yonekawa and Shimpei Sato and Hiroki Nakahara and Masayuki Ikebe and Shinya Takamaeda-Yamazaki and Tetsuya Asai and Tadahiro Kuroda and Masato Motomura},
  title = {In-Memory Area-Efficient Signal Streaming Processor Design for Binary Neural Networks},
  booktitle = {},
  year = 2017,
}

@inproceedings{CTT100743027,
  author = {Kota Ando and Haruyoshi Yonekawa and Shimpei Sato and Hiroki Nakahara and Masato Motomura},
  title = {BRein memory: a 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS},
  booktitle = {},
  year = 2017,
}

@inproceedings{CTT100743026,
  author = {Haruyoshi Yonekawa and Hiroki Nakahara},
  title = {An On-chip Memory Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA},
  booktitle = {},
  year = 2017,
}

@inproceedings{CTT100743028,
  author = {Hiroki Nakahara and Akira Jinguji and Shimpei Sato and Tsutomu Sasao},
  title = {A Random Forest using a Multi-valued Decision Diagram on an FPGA},
  booktitle = {},
  year = 2017,
}

@inproceedings{CTT100743029,
  author = {Tomoya Fujii and Shimpei Sato and Hiroki Nakahara and Masato Motomura},
  title = {An FPGA Realization of a Deep Convolutional Neural Network using a Threshold Neuron Pruning},
  booktitle = {},
  year = 2017,
}

@inproceedings{CTT100743030,
  author = {Hiroki Nakahara and Haruyoshi Yonekawa and Hisashi Iwamoto and Masato Motomura},
  title = {A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA},
  booktitle = {},
  year = 2017,
}

@inproceedings{CTT100743034,
  author = {神宮司明良 and 佐藤真平 and 中原啓貴},
  title = {特徴空間の分割にk平均法を導入したランダムフォレストのFPGA実装},
  booktitle = {},
  year = 2017,
}

@inproceedings{CTT100743033,
  author = {米川 晴義 and 中原 啓貴 and 本村 真人},
  title = {ディープニューラルネットワークの2値化と3値化の比較},
  booktitle = {},
  year = 2017,
}

@inproceedings{CTT100743032,
  author = {藤井智也 and 佐藤真平 and 中原啓貴 and 本村真人},
  title = {畳込みニューラルネットワークのニューロン刈りによるメモリ量削減とFPGA実現について},
  booktitle = {},
  year = 2017,
}

@inproceedings{CTT100743031,
  author = {米川晴義 and 中原啓貴 and 本村真人},
  title = {電力性能効率に優れた二値化ディープニューラルネットワークのFPGA実装},
  booktitle = {},
  year = 2017,
}

@misc{CTT100743025,
  author = {中原 啓貴 and 井上 一成 and 中田 秀基},
  title = {ネットワーク検索エンジン及びディープニューラルネットワークの高速化},
  year = 2017,
}

@misc{CTT100802481,
  author = {中原啓貴},
  title = {ニューラルネットワーク回路装置、ニューラルネットワーク、ニューラルネットワーク処理方法およびニューラルネットワークの実行プログラム},
  howpublished = {登録特許},
  year = 2021,
  month  = {},
  note   = {特願2017-180457(2017/09/20), 特開2019-057072(2019/04/11), 特許第6933367号(2021/08/23)}
}


@misc{CTT100756302,
  author = {中原啓貴 and 米川晴義},
  title = {ニューラルネットワーク回路装置、ニューラルネットワーク、ニューラルネットワーク処理方法およびニューラルネットワークの実行プログラム},
  howpublished = {登録特許},
  year = 2017,
  month  = {},
  note   = {特願2016-235383(2016/12/02), 特開2018-092377(2018/06/14), 特許第6183980号(2017/08/04)}
}