Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization

Publication Information

Title

Japanese:
English:	Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization

Author

Japanese:	小平行秀, 高橋篤司.
English:	Yukihide Kohira, Atsushi Takahashi.

Language

English

Journal/Book name

Japanese:
English:	IEICE Trans. Fundamentals

Volume, Number, Page

Vol. E90-A No. 4 pp. 800-807

Published date

Apr. 1, 2007

Publisher

Japanese:
English:

Conference name

Japanese:
English:

Conference site

Japanese:
English:

File

DOI