Low Power Track and Hold Circuit Design Based on Two-stage Configuration

Publication Information

Title

Japanese:
English:	Low Power Track and Hold Circuit Design Based on Two-stage Configuration

Author

Japanese:	Isamu Matsumoto, 佐藤隆英, 高木茂孝, 藤井信生.
English:	Isamu Matsumoto, Takahide Sato, Shigetaka Takagi, Nobuo Fujii.

Language

English

Journal/Book name

Japanese:
English:	Proc. IEEJ 2006 International Analog VLSI Workshop

Volume, Number, Page

Vol. CD-ROM

Published date

Nov. 2006

Publisher

Japanese:
English:

Conference name

Japanese:
English:	2006 IEEJ International Analog VLSI Workshop

Conference site

Japanese:
English:	Hangzhou, China