A Low-Latency and High-Power-Efficient On-Chip LVDS Transmission Line Interconnect for an RC Interconnect Alternative

Publication Information

Title

Japanese:
English:	A Low-Latency and High-Power-Efficient On-Chip LVDS Transmission Line Interconnect for an RC Interconnect Alternative

Author

Japanese:	伊藤浩之, Junki Seita, 石井隆宏, Hideyuki Sugita, 岡田健一, 益一哉.
English:	Hiroyuki Ito, Junki Seita, Takahiro Ishii, Hideyuki Sugita, Kenichi Okada, Kazuya Masu.

Language

English

Journal/Book name

Japanese:
English:

Volume, Number, Page

pp. 193-195

Published date

June 2007

Publisher

Japanese:
English:

Conference name

Japanese:
English:	IEEE International Interconnect Technology Conference (IITC)

Conference site

Japanese:
English:	San Francisco