A 8-Gbps Low-Latency Multi-Drop On-Chip Transmission Line Interconnect with 1.2-mW Two-Way Transceivers

Publication Information

Title

Japanese:
English:	A 8-Gbps Low-Latency Multi-Drop On-Chip Transmission Line Interconnect with 1.2-mW Two-Way Transceivers

Author

Japanese:	伊藤浩之, Makoto Kimura, 岡田健一, 益一哉.
English:	Hiroyuki Ito, Makoto Kimura, Kenichi Okada, Kazuya Masu.

Language

English

Journal/Book name

Japanese:
English:

Volume, Number, Page

pp. 136-137

Published date

June 2007

Publisher

Japanese:
English:

Conference name

Japanese:
English:	IEEE Symposium on VLSI Circuits

Conference site

Japanese:
English:	Kyoto