On-Chip Global Interconnect Using Transmission Line | Tokyo Tech Research Repository (T2R2)

Publication Information

Title

Japanese:
English:	On-Chip Global Interconnect Using Transmission Line

Author

Japanese:	益一哉.
English:	Kazuya Masu.

Language

English

Journal/Book name

Japanese:
English:

Volume, Number, Page

Published date

Dec. 2007

Publisher

Japanese:
English:

Conference name

Japanese:
English:	The 2nd Workshop on Interconnect Design and Variablity(IDV2007)

Conference site

Japanese:
English:	Bangalore,India

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