LVDS-type On-Chip Transmision Line Interconnect with Passive Equalizers in 90 nm CMOS Process

Publication Information

Title

Japanese:
English:	LVDS-type On-Chip Transmision Line Interconnect with Passive Equalizers in 90 nm CMOS Process

Author

Japanese:	峰山亜希子, 伊藤浩之, 石井隆宏, 岡田健一, 益一哉.
English:	Akiko Mineyama, Hiroyuki Ito, Takahiro Ishii, Kenichi Okada, Kazuya Masu.

Language

English

Journal/Book name

Japanese:
English:	IEEE/ACM Asia and South Pacific Design Automation Conference (Design Contest)

Volume, Number, Page

Published date

Jan. 2008

Publisher

Japanese:
English:

Conference name

Japanese:
English:	IEEE/ACM Asia and South Pacific Design Automation Conference (Design Contest)

Conference site

Japanese:
English:	Seoul, South Korea

DOI