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Title
Japanese: 
English:A Sub-1mW 5.5-GHz PLL with Digitally-Calibrated ILFD and Linearized Varactor for Low Supply Voltage Operation 
Author
Japanese: 池田 翔, 上村 龍也, 李 尚曄, 伊藤 浩之, 石原 昇, 益 一哉.  
English: Sho Ikeda, Tatsuya Kamimura, Sangyeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu.  
Language English 
Journal/Book name
Japanese: 
English: 
Volume, Number, Page        
Published date 2013 
Publisher
Japanese: 
English: 
Conference name
Japanese: 
English:IEEE Radio Frequency Integrated Circuit 2013 
Conference site
Japanese: 
English:Seattle 
Official URL http://www.rfic-ieee.org/
 
Abstract This paper proposes an ultra-low-power 5.5-GHz PLL which employs a divide-by-4 injection-locked frequency divider (ILFD) and linearity-compensated varactor for low supply voltage operation. The digital calibration circuit is introduced to control the ILFD frequency automatically. The proposed varactor, which applies a forwardbody-bias (FBB) technique, is employed for linear-frequencytuning under the power supply of 0.5V. The proposed PLL was fabricated in 65nm CMOS. With a 34.3-MHz reference, it shows a 1-MHz-offset phase noise of 〓106 dBc/Hz, a reference spur level lower than 〓65 dBc,and the total power consumption of 950 W at 5.5 GHz.

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