A High-speed Verilog HDL Simulation Method using a Lightweight Translator

Publication Information

Title

Japanese:
English:	A High-speed Verilog HDL Simulation Method using a Lightweight Translator

Author

Japanese:	小林諒平, 味曽野智礼, 吉瀬謙二.
English:	Ryohei Kobayashi, Tomohiro Misono, Kenji Kise.

Language

English

Journal/Book name

Japanese:
English:

Volume, Number, Page

pp. 29-34

Published date

July 25, 2016

Publisher

Japanese:
English:

Conference name

Japanese:
English:	International Symposium on High-Efficient Accelerators ajd Reconfigurable Technologies (Heart 2016)

Conference site

Japanese:
English: