A 265-µW Fractional-N Digital PLL with Seamless Automatic Switching Sub-sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS

Publication Information

Title

Japanese:
English:	A 265-µW Fractional-N Digital PLL with Seamless Automatic Switching Sub-sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS

Author

Japanese:	Liu Hanli, SUN Zheng, HUANG Hongye, Deng Wei, SIRIBURANON T, Pang Jian, Wang Yun, ｳｰﾙｲ, 染谷晃基, 白根篤史, 岡田健一.
English:	Hanli Liu, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, Kenichi Okada.

Language

English

Journal/Book name

Japanese:
English:	IEEE Journal of Solid-State Circuits (JSSC)

Volume, Number, Page

Vol. 54 No. 12 pp. 3478-3492

Published date

Dec. 2019

Publisher

Japanese:
English:

Conference name

Japanese:
English:

Conference site

Japanese:
English: