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Publication Information
Title
Japanese:
English:
A 265-µW Fractional-N Digital PLL with Seamless Automatic Switching Sub-sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS
Author
Japanese:
Liu Hanli
,
SUN Zheng
,
HUANG Hongye
,
Deng Wei
,
SIRIBURANON T
,
Pang Jian
,
Wang Yun
,
ウー ルイ
, 染谷 晃基,
白根 篤史
,
岡田 健一
.
English:
Hanli Liu
,
Zheng Sun
,
Hongye Huang
,
Wei Deng
,
Teerachot Siriburanon
,
Jian Pang
,
Yun Wang
,
Rui Wu
, Teruki Someya,
Atsushi Shirane
,
Kenichi Okada
.
Language
English
Journal/Book name
Japanese:
English:
IEEE Journal of Solid-State Circuits (JSSC)
Volume, Number, Page
Vol. 54 No. 12 pp. 3478-3492
Published date
Dec. 2019
Publisher
Japanese:
English:
Conference name
Japanese:
English:
Conference site
Japanese:
English:
©2007
Tokyo Institute of Technology All rights reserved.