Nonvolatile flip-flop based on pseudo-spin-transistor architecture and its nonvolatile power-gating applications for low-power CMOS logic

Publication Information

Title

Japanese:
English:	Nonvolatile flip-flop based on pseudo-spin-transistor architecture and its nonvolatile power-gating applications for low-power CMOS logic

Author

Japanese:	山本修一郎, Shuto, Y., Sugahara, S..
English:	Shuichiro Yamamoto, Shuto, Y., Sugahara, S..

Language

English

Journal/Book name

Japanese:
English:	EPJ Applied Physics

Volume, Number, Page

Vol. 63 No. 1

Published date

2013

Publisher

Japanese:
English:

Conference name

Japanese:
English:

Conference site

Japanese:
English:

DOI