A 265-µW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS

Publication Information

Title

Japanese:
English:	A 265-µW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS

Author

Japanese:	Hanli Liu, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, 染谷晃基, 白根篤史, 岡田健一.
English:	Hanli Liu, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Pang Jian, Yun Wang, Rui Wu, 染谷晃基, Atsushi Shirane, Kenichi Okada.

Language

English

Journal/Book name

Japanese:
English:

Volume, Number, Page

Published date

Mar. 4, 2019

Publisher

Japanese:
English:

Conference name

Japanese:	IEEE SSCS Japan Chapter ISSCC報告会
English:

Conference site

Japanese:	兵庫県神戸
English: