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Title
Japanese: 
English:Scaling limit for InGaAs/GaAsSb heterojunction double-gate tunnel FETs from the viewpoint of direct band-to-band tunneling from source to drain induced off-characteristics deterioration 
Author
Japanese: 林 文博, 岩田 真次郎, 福田 浩一, 宮本 恭幸.  
English: Wenbo Lin, Shinjiro Iwata, Koichi Fukuda, Yasuyuki Miyamoto.  
Language English 
Journal/Book name
Japanese: 
English:Japanese Journal of Applied Physics 
Volume, Number, Page Vol. 55    No. 7    pp. 070303
Published date June 2016 
Publisher
Japanese: 
English: 
Conference name
Japanese: 
English: 
Conference site
Japanese: 
English: 
Official URL https://doi.org/10.7567/jjap.55.070303
 
DOI https://doi.org/10.7567/jjap.55.070303
Abstract <jats:title>Abstract</jats:title> <jats:p>In this paper, we propose a method to classify the tunneling currents using simulations. The main objective is to investigate the effects of the direct source-to-drain tunneling, which is undesirable, in the case of devices with extremely short channels. We performed the classification of tunneling currents in InGaAs/GaAsSb heterojunction double-gate tunnel FETs based on this method, and we found that the direct-tunneling component increased dramatically in short-channel cases. The channel length must be 20 nm or longer, in case of InGaAs/GaAsSb heterojunction double-gate tunnel FETs, to limit the off-current within 10 pA/µm, which is required as per the ITRS LP.</jats:p>

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