Two-layer Bottleneck Channel Track Assignment for Analog VLSI

Publication Information

Title

Japanese:
English:	Two-layer Bottleneck Channel Track Assignment for Analog VLSI

Author

Japanese:	谷口和弥, 田湯智, 高橋篤司, モロンゴマチュー, 南誠, 西岡克也.
English:	Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi, Mathieu Molongo, Makoto Minami, Katsuya Nishioka.

Language

English

Journal/Book name

Japanese:
English:	IPSJ Trans. on System LSI Design Methodology

Volume, Number, Page

Vol. 17 pp. 67-76

Published date

June 19, 2024

Publisher

Japanese:
English:

Conference name

Japanese:
English:

Conference site

Japanese:
English:

Official URL

DOI