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Publication Information
Title
Japanese:
English:
A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter
Author
Japanese:
XU Dingxin
,
LIU Zezheng
,
KUAI Yifeng
,
HUANG Hongye
,
Zhang Yuncheng
,
Sun Zheng
,
Liu Bangan
,
Wang Wenqian
,
XIONG Yuang
,
Qiu Junjun
,
MADANY Waleed Mahmoud Mohamed
,
ZHANG Yi
,
Fadila Ashbir Aviat
,
白根 篤史
,
岡田 健一
.
English:
Dingxin Xu
,
Zezheng Liu
,
Yifeng Kuai
,
Hongye Huang
,
Yuncheng Zhang
,
Zheng Sun
,
Bangan Liu
,
Wenqian Wang
,
Yuang Xiong
,
Junjun Qiu
,
Waleed Madany
,
Yi Zhang
,
Ashbir Aviat Fadila
,
Atsushi Shirane
,
Kenichi Okada
.
Language
English
Journal/Book name
Japanese:
English:
Volume, Number, Page
Published date
Feb. 2024
Publisher
Japanese:
English:
Conference name
Japanese:
English:
IEEE International Solid-State Circuits Conference (ISSCC)
Conference site
Japanese:
English:
San Francisco
©2007
Tokyo Institute of Technology All rights reserved.