A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter

Publication Information

Title

Japanese:
English:	A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter

Author

Language

English

Journal/Book name

Japanese:
English:

Volume, Number, Page

Published date

Feb. 2024

Publisher

Japanese:
English:

Conference name

Japanese:
English:	IEEE International Solid-State Circuits Conference (ISSCC)

Conference site

Japanese:
English:	San Francisco