Integrated Testing Strategy of Wafer and Chip-level Characterization for  Photonic Integrated Circuits

Publication Information

Title

Japanese:
English:	Integrated Testing Strategy of Wafer and Chip-level Characterization for Photonic Integrated Circuits

Author

Japanese:	Eissa Moataz, 堀川剛, 吉田俊, 西山伸彦.
English:	Moataz Eissa, Tsuyoshi Horikawa, Suguru Yoshida, Nobuhiko Nishiyama.

Language

English

Journal/Book name

Japanese:
English:

Volume, Number, Page

Published date

July 2025

Publisher

Japanese:
English:

Conference name

Japanese:
English:	30th OptoElectronics and Communications Conference

Conference site

Japanese:
English:	Sapporo Convention Center