We model grain boundaries (GBs) for polycrystalline ZnO thin film transistors (TFTs). Experimental result shows a non-linear increase of drain current and gradual enhancement of field effect mobility with increasing gate bias. Our initial single GB model was unable to explain the experimentally obtained results, where we considered the peak defect distribution at the mid gap. Realizing from the experimentally obtained results, we remodeled the grain boundary considering the peak distribution close to the conduction band, which then better replicates the experimental observation. We describe here the transfer characteristic of experimental ZnO TFT in linear region with calculated potential profiles. Appropriate grain boundary modeling signifies that the slower decrease in potential barrier in grain boundary with applied gate voltage is responsible for such non-linear changes in drain current and gradual enhancement of mobility.
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