In this paper, an ultra-low-power 5.5-GHz PLL is
proposed which employs the new divide-by-4 injection-locked
frequency divider (ILFD) and a class-C VCO for operation under
a power supply of 0.5V. A forward-body-biasing (FBB) technique
can decrease threshold voltage of MOS transistors, which can
improve operation frequency and can widen the lock range of
the ILFD. The double-switch injection technique is also proposed
to widen the lock range of the ILFD.
The proposed PLL was fabricated in 65nm CMOS. The whole
circuit consumes 1.6mW under the power supply of 0.5V. With
a 34.6-MHz reference, it shows a 1-MHz-offset phase noise of
〓105 dBc/Hz and a reference spur level lower than 〓65 dBc at
5.5 GHz.
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