This paper proposes an ultra-low-power 5.5-GHz PLL which employs a divide-by-4 injection-locked frequency divider (ILFD) and linearity-compensated varactor for low supply voltage operation. The digital calibration
circuit is introduced to control the ILFD frequency automatically.
The proposed varactor, which applies a forwardbody-bias (FBB) technique, is employed for linear-frequencytuning
under the power supply of 0.5V.
The proposed PLL was fabricated in 65nm CMOS. With a 34.3-MHz reference, it shows a 1-MHz-offset phase noise of 〓106 dBc/Hz, a reference spur level lower than 〓65 dBc,and the total power consumption of 950 W at 5.5 GHz.
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