論文

• Yiqiang Sheng, Atsushi Takahashi. A Novel High-Performance Heuristic Algorithm with Application to Physical Design Optimization, IEICE Trans. Fundamentals, Vol. E97-A, No. 12, pp. 2418-2426, Dec. 2014.
• Yiqiang Sheng, Atsushi Takahashi. A New Variation of Adaptive Simulated Annealing for 2D/3D Packing Optimization, IPSJ Trans. on System LSI Design Methodology, Vol. 6, pp. 94-100, Aug. 2013.  公式リンク  
  

著書

• Yiqiang Sheng, Atsushi Takahashi. A Simulated Annealing Based Approach to Integrated Circuit Layout Design, Simulated Annealing - Single and Multiple Objective Problems, InTech, pp. 239-260, Oct. 2012.  公式リンク  

国際会議発表 (査読有り)

• Yiqiang Sheng, Atsushi Takahashi, Shuichi Ueno. 2-Stage Simulated Annealing with Crossover Operator for 3D-Packing Volume Minimization, Proc. the 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012), pp. 227-232, Mar. 2012.  公式リンク  
  
• Yiqiang Sheng, Atsushi Takahashi, Shuichi Ueno. RRA-Based Multi-Objective Optimization to Mitigate the Worst Cases of Placement, Proc. IEEE 9th International Conference on ASIC (ASICON 2011), pp. 357-360, Oct. 2011.
• Yiqiang Sheng, Atsushi Takahashi, Shuichi Ueno. Relay-Race Algorithm: A Novel Heuristic Approach to VLSI/PCB Placement, Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2011), pp. 96-101, July 2011.

国内会議発表 (査読有り)

• Yiqiang Sheng, Atsushi Takahashi, Shuichi Ueno. A Stochastic Optimization Method to Solve General Placement Problem Effectively, Proc. DA Symposium 2011, IPSJ Symposium Series, Vol. 2011, No. 5, pp. 27-32, Aug. 2011.

国内会議発表 (査読なし・不明)

• Yiqiang Sheng, Atsushi Takahashi, Shuichi Ueno. An Improved Simulated Annealing for 3D Packing with Sequence Triple and Quintuple Representations, Technical Committee on VLSI Design Technologies, IEICE Technical Report (VLD2011-88), Vol. 111, No. 324, pp. 209-214, Nov. 2011.  公式リンク  
  
• Yiqiang Sheng, Atsushi Takahashi, Shuichi Ueno. MSA: Mixed Stochastic Algorithm for Placement with Larger Solution Space, Technical Committee on VLSI Design Technologies, IEICE Technical Report (VLD2011-42), Vol. 111, No. 216, pp. 11-16, Sept. 2011.

学位論文

• High-Performance Heuristics with Applications to 2D/3D IC Physical Design Optimization,  Exam Summary,  Doctor (Engineering),  Tokyo Institute of Technology,  2014/07/31,   
• High-Performance Heuristics with Applications to 2D/3D IC Physical Design Optimization,  Summary,  Doctor (Engineering),  Tokyo Institute of Technology,  2014/07/31,   
• High-Performance Heuristics with Applications to 2D/3D IC Physical Design Optimization,  Thesis,  博士（工学）,  Tokyo Institute of Technology,  2014/07/31,   

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