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中原啓貴 2017年 研究業績一覧 (16件 / 80件)
国際会議発表 (査読有り)
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Masayuki Shimoda,
Shimpei Sato,
Hiroki Nakahara.
All Binarized Convolutional Neural Network and Its implementation on an FPGA,
The International Conference on Field-Programmable Technology (FPT 2017),
pp. 291-294,
Dec. 2017.
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Hiroki Nakahara,
Haruyoshi Yonekawa,
Shimpei Sato.
An Object Detector based on Multiscale Sliding Window Search using a Fully Pipelined Binarized CNN on an FPGA,
The International Conference on Field-Programmable Technology (FPT 2017),
pp. 168-175,
Dec. 2017.
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Hiroki Nakahara,
Tomoya Fujii,
Shimpei Sato.
A Fully Connected Layer Elimination for a Binarized Convolutional Neural Network on an FPGA,
The 27th International Conference on Field-programmable Logic and Applications (FPL 2017),
pp. 1-4,
Sept. 2017.
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Hiroki Nakahara,
Haruyoshi Yonekawa,
Tomoya Fujii,
Masayuki Shimoda,
Shimpei Sato.
GUINNESS: A GUI based neural network synthesizer for an FPGA,
The 27th International Conference on Field-programmable Logic and Applications (FPL 2017),
Sept. 2017.
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Kota Ando,
Kodai Ueyoshi,
Kazutoshi Hirose,
Kentaro Orimo,
Haruyoshi Yonekawa,
Shimpei Sato,
Hiroki Nakahara,
Masayuki Ikebe,
Shinya Takamaeda-Yamazaki,
Tetsuya Asai,
Tadahiro Kuroda,
Masato Motomura.
In-Memory Area-Efficient Signal Streaming Processor Design for Binary Neural Networks,
The 60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2017),
pp. 116-119,
Aug. 2017.
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Kota Ando,
Haruyoshi Yonekawa,
Shimpei Sato,
Hiroki Nakahara,
Masato Motomura.
BRein memory: a 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS,
2017 Symposia on VLSI Technology and Circuits,
June 2017.
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Haruyoshi Yonekawa,
Hiroki Nakahara.
An On-chip Memory Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA,
24th Reconfigurable Architectures Workshop (RAW 2017),
May 2017.
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Hiroki Nakahara,
Akira Jinguji,
Shimpei Sato,
Tsutomu Sasao.
A Random Forest using a Multi-valued Decision Diagram on an FPGA,
The 47th IEEE International Symposium on Multiple-valued Logic (ISMVL 2017),
May 2017.
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Tomoya Fujii,
Shimpei Sato,
Hiroki Nakahara,
Masato Motomura.
An FPGA Realization of a Deep Convolutional Neural Network using a Threshold Neuron Pruning,
International Symposium on Applied Reconfigurable Computing (ARC2017),
Apr. 2017.
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Hiroki Nakahara,
Haruyoshi Yonekawa,
Hisashi Iwamoto,
Masato Motomura.
A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA,
International Symposium on Field-Programmable Gate Array (FPGA2017),
Feb. 2017.
国内会議発表 (査読なし・不明)
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神宮司明良,
佐藤真平,
中原啓貴.
特徴空間の分割にk平均法を導入したランダムフォレストのFPGA実装,
第30回多値論理とその応用研究会,
Jan. 2017.
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米川 晴義,
中原 啓貴,
本村 真人.
ディープニューラルネットワークの2値化と3値化の比較,
多値論理研究会,
Jan. 2017.
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藤井智也,
佐藤真平,
中原啓貴,
本村真人.
畳込みニューラルネットワークのニューロン刈りによるメモリ量削減とFPGA実現について,
電子情報通信学会リコンフィギャラブルシステム研究会,
Jan. 2017.
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米川晴義,
中原啓貴,
本村真人.
電力性能効率に優れた二値化ディープニューラルネットワークのFPGA実装,
電子情報通信学会リコンフィギャラブルシステム研究会,
Jan. 2017.
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