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Publication List - Kazuya Taniguchi (7 entries)
- 2019
- 2018
- 2017
- 2016
- 2015
- All
Journal Paper
International Conference (Reviewed)
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Kazuya Taniguchi,
Satoshi Tayu,
Atsushi Takahashi,
Mathieu Molongo,
Makoto Minami,
Katsuya Nishioka.
A Fast Three-layer Bottleneck Channel Track Assignment with Layout Constraints using ILP,
Proc. the 25th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2024),
pp. 50-55,
Mar. 2024.
Official location Official location
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Kazuya Taniguchi,
Satoshi Tayu,
Atsushi Takahashi,
Yukichi Todoroki,
Makoto Minami.
Bottleneck Channel Routing to Reduce the Area of Analog VLSI,
Proc. the 24th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2022),
pp. 26-31,
Oct. 2022.
Official location Official location
Domestic Conference (Reviewed)
Domestic Conference (Not reviewed / Unknown)
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Kazuya Taniguchi,
Satoshi Tayu,
Atsushi TAKAHASHI,
モロンゴ マチュー,
Makoto Minami,
西岡克也.
Three-layer Bottleneck Channel Track Assignment for Pins Placed on Opposite Sides,
Technical Committee on VLSI Design Technologies,
IEICE Technical Report (VLD2023-103),
Vol. 123,
No. 390,
pp. 24-29,
Feb. 2024.
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Kazuya Taniguchi,
Satoshi Tayu,
Atsushi Takahashi,
Molongo Mathieu,
Makoto Minami,
Katsuya Nishioka.
Track Assignment considering Routing Crossing Relations to Improve Feasibility in Bottleneck Channel Routing,
Technical Committee on VLSI Design Technologies,
IEICE Technical Report (VLD2022-101),
Vol. 122,
No. 402,
pp. 149-154,
Mar. 2023.
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Kazuya Taniguchi,
Satoshi Tayu,
Atsushi Takahashi,
Yukichi Todoroki,
Makoto Minami.
Bottleneck Channel Routing to Reduce the Area of Analog VLSI,
Technical Committee on VLSI Design Technologies,
IEICE Technical Report (VLD2021-77),
Vol. 121,
No. 412,
pp. 7-12,
Mar. 2022.
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