|
Publication List - Makoto Minami (9 entries)
![2024 2024](/ls_arrow.gif)
![2019 2019](/ll_arrow.gif)
![2015 2015](/l_arrow.gif)
- 2014
- 2013
- 2012
- 2011
- 2010
![2013 2013](/r_arrow.gif)
![2009 2009](/rr_arrow.gif)
- All
Journal Paper
International Conference (Reviewed)
-
Kazuya Taniguchi,
Satoshi Tayu,
Atsushi Takahashi,
Mathieu Molongo,
Makoto Minami,
Katsuya Nishioka.
A Fast Three-layer Bottleneck Channel Track Assignment with Layout Constraints using ILP,
Proc. the 25th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2024),
pp. 50-55,
Mar. 2024.
Official location
Official location
-
Kazuya Taniguchi,
Satoshi Tayu,
Atsushi Takahashi,
Yukichi Todoroki,
Makoto Minami.
Bottleneck Channel Routing to Reduce the Area of Analog VLSI,
Proc. the 24th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2022),
pp. 26-31,
Oct. 2022.
Official location
Official location
Domestic Conference (Reviewed)
-
Kazuya Taniguchi,
Satoshi Tayu,
Atsushi Takahashi,
Molongo Mathieu,
Makoto Minami,
Katsuya Nishioka.
Three-layer Bottleneck Channel Track Assignment by ILP,
Proc. DA Symposium 2023, IPSJ Symposium Series,
pp. 199-206,
Aug. 2023.
Official location
-
Zuan Jo,
Satoshi Tayu,
Atsushi Takahashi,
Molongo Mathieu,
Makoto Minami,
Katsuya Nishioka.
Pair Symmetrical Routing in Common Centroid Placement with Double Via Constraints,
Proc. DA Symposium 2023, IPSJ Symposium Series,
pp. 207-212,
Aug. 2023.
Official location
Domestic Conference (Not reviewed / Unknown)
-
Zuan Jiyo,
Satoshi Tayu,
Atsushi Takahashi,
Mathieu Molongo,
Makoto Minami,
Katsuya Nishioka.
A Template Routing Method Using SMT Solver for Double Via-Constrained Pair Symmetric Routing Problem,
Technical Committee on VLSI Design Technologies,
IEICE Technical Report (VLD2023-102),
Vol. 123,
No. 390,
pp. 18-23,
Feb. 2024.
-
Kazuya Taniguchi,
Satoshi Tayu,
Atsushi TAKAHASHI,
モロンゴ マチュー,
Makoto Minami,
西岡克也.
Three-layer Bottleneck Channel Track Assignment for Pins Placed on Opposite Sides,
Technical Committee on VLSI Design Technologies,
IEICE Technical Report (VLD2023-103),
Vol. 123,
No. 390,
pp. 24-29,
Feb. 2024.
-
Kazuya Taniguchi,
Satoshi Tayu,
Atsushi Takahashi,
Molongo Mathieu,
Makoto Minami,
Katsuya Nishioka.
Track Assignment considering Routing Crossing Relations to Improve Feasibility in Bottleneck Channel Routing,
Technical Committee on VLSI Design Technologies,
IEICE Technical Report (VLD2022-101),
Vol. 122,
No. 402,
pp. 149-154,
Mar. 2023.
-
Zuan Jo,
Satoshi Tayu,
Atsushi Takahashi,
Molongo Mathieu,
Makoto Minami,
Katsuya Nishioka.
Pair Symmetrical Routing in Common Centroid Placement with Common Signal Constraints,
Technical Committee on VLSI Design Technologies,
IEICE Technical Report (VLD2022-102),
Vol. 122,
No. 402,
pp. 155-160,
Mar. 2023.
[ Save as BibTeX ]
[ Paper, Presentations, Books, Others, Degrees: Save as CSV
]
[ Patents: Save as CSV
]
|