論文

• Satoru Jimbo, Daiki Okonogi, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura. A Hybrid Integer Encoding Method for Obtaining High-quality Solutions of Quadratic Knapsack Problems on Solid-state Annealers, IEICE Transactions on Information and Systems, Vol. E105-D, No. 12, Dec. 2022.
• Kazutoshi Hirose, Jaehoon Yu, Kota Ando, Yasuyuki Okoshi, Angel Lopez Garcia-Arias, Junnosuke Suzuki, Thiem Van Chu, Kazushi Kawamura, Masato Motomura. Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet, International Solid-State Circuits Conference, Feb. 2022.
• Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu. ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training, International Journal of Networking and Computing, July 2021.
• Junnosuke Suzuki, Tomohiro Kaneko, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu. ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation, International Journal of Networking and Computing, July 2021.
• Thiem Van Chu, Kenji Kise, Kiyofumi Tanaka. Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs, Proceedings of the 28th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), pp. 211-221, Feb. 2020.
• Thiem Van Chu, Kenji Kise. LEF: An Effective Routing Algorithm for Two-Dimensional Meshes, IEICE transactions on information and systems, vol. E102-D, no. 10, pp. 1925-1941, Oct. 2019.
• Thiem Van Chu, Shimpei Sato, Kenji Kise. Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA, ACM Transactions on Reconfigurable Technology and Systems (TRETS), Vol. 10, No. 4, pp. 1-27, Dec. 2017.

国際会議発表 (査読有り)

• Yasuyuki Okoshi, Angel Lopez Garcia-Arias, Kazutoshi Hirose, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu. Multicoated Supermasks Enhance Hidden Networks, International Conference on Machine Learning, July 2022.
• Thiem Van Chu, Ryuichi Kitajima, Kazushi Kawamura, Jaehoon Yu, Masato Motomura. A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning, International Conference on Field-Programmable Technology, Dec. 2021.
• Kota Ando, Jaehoon Yu, Kazutoshi Hirose, Hiroki Nakahara, Kazushi Kawamura, Thiem Van Chu, Masato Motomura. Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner, Hot Chips, Aug. 2021.
• Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu. ExtraFerns: Fully Parallel Ensemble Learning Technique with Non-Greedy yet Minimal Memory Access Training, International Symposium on Computing and Networking (CANDAR), Nov. 2020.
• Junnosuke Suzuki, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu. ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation, International Symposium on Computing and Networking (CANDAR), Nov. 2020.
• Thiem Van Chu, Kenji Kise. An Effective Architecture for Trace-Driven Emulation of Networks-on-Chip on FPGAs, 28th International Symposium on Field-Programmable Logic and Applications (FPL 2018), pp. 419-426, Aug. 2018.
• Makoto Saitoh, Elsayed A. Elsayed, Thiem Van Chu, Susumu Mashimo, Kenji Kise. A High-Performance and Cost-Effective Hardware Merge Sorter without Feedback Datapath, IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2018), pp. 197-204, Apr. 2018.
• Thiem Van Chu, Myeonggu Kang, Shi FA, Kenji Kise. Enhanced Long Edge First Routing Algorithm and Evaluation in Large-Scale Networks-on-Chip, IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2017), pp. 83-90, Sept. 2017.
• Susumu Mashimo, Thiem Van Chu, Kenji Kise. High-Performance Hardware Merge Sorter, IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2017), Proceedings IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines FCCM 2017, IEEE, pp. 1-8, Apr. 2017.
• Takuma Usui, Thiem Van Chu, Kenji Kise. A Cost-effective and Scalable Merge Sorter Tree pm FPGAs, International Symposium on Computing and Networking (CANDAR'16), Nov. 2016.
• Masashi Imai, Thiem Van Chu, Kenji Kise, Tomohiro Yoneda. The Synchronous vs. Asynchronous NoC Routers: An Apple-to-Apple Comparison between Synchronous and Transition Signaling Asynchronous Designs,, IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016), Sept. 2016.
• Susumu Mashimo, Thiem Van Chu, Kenji Kise. Cost-Effective and High-Throughput Merge Network Architecture for the Fastest FPGA Sorting Accelerator, International Symposium on High-Efficient Accelerators ajd Reconfigurable Technologies (Heart 2016), pp. 7-12, July 2016.
• Thiem Van Chu, Shimpei Sato, Kenji Kise. Ultra-Fast NoC Emulation on a Single FPGA, The 25th International Conference on Field Programmable Logic and Applications (FPL 2015), Sept. 2015.
• Thiem Van Chu, Shimpei Sato, Kenji Kise. Enabling Fast and Accurate Emulation of Large-scale Network on Chip Architectures on an Single FPGA (short paper), The 23rd IEEE International Symposium on Field-Programmable Custrom Conputing Machines (FCCM 2015), pp. 60-63, May 2015.
• Thiem Van Chu, Shimpei Sato, Kenji Kise. KNoCEmu: High Speed FPGA-Emulator fir a Kilo-Node Scale NoC, IEEE 8th International Symposium on Embedded Multicore SoCs (MCSoC-14), pp. 215-222, Sept. 2014.

国際会議発表 (査読なし・不明)

• Hiroshi Nakatsuka, Yuichiro Tanaka, Thiem Van Chu, Shinya Takamaeda-Yamazaki, Kenji Kise. Ultrasmall: The Smallest MIPS Soft Processor, 24th International conference on Field Programmable Logic and Applications(FPL2014), pp. 1-4, Sept. 2014.

国内会議発表 (査読なし・不明)

• Aye Myat Mon, Thiem Van Chu, Kiyofumi Tanaka. A Study of Real-Time Extension for RISC-V Processors, 研究報告組込みシステム（EMB）, vol. 2019-EMB-51, no. 7, pp. 1-2, June 2019.
• Jiajun Guo, Amr Ashmawy, Thiem Van Chu, Kiyofumi Tanaka. High-Accuracy and Cost-Effective Neural Networks for Embedded Systems, 研究報告組込みシステム（EMB）, vol. 2019-EMB-50, no. 36, pp. 1-8, Mar. 2019.
• Thiem Chu Van, Kenji Kise. Trace-Driven Emulation of Large-Scale Networks-on-Chip on FPGAs, IEICE RECONF2016-74, pp. 153-158, Jan. 2017.
• 齋藤 誠, 眞下 達, Chu Van Thiem, 吉瀬 謙二. FPGAを用いたソーティングアクレラレータのためのマージネットワークの改良, 電子情報通信学会研究報告RECONF2016-42, pp. 13-18, Nov. 2016.
• Chu Van Thiem, 吉瀬 謙二. FPGAを用いたFat TreeベースNoCの高速エミュレーション, 電子情報通信学会研究報告 CPSY2016-24, pp. 161-166, Aug. 2016.
• Robin Kase, Thiem Van Chu, Kenji Kise. Efficient Use Space Scheduler Library for FreeRTOS, 情報処理学会第７８回全国大会, Mar. 2016.
• Thiem Van Chu, Kenji Kise. Enabling Fast Thousand-Core Processor Emulation using FPGAs, 情報処理学会第７８回全国大会, Mar. 2016.
• Thiem Van Chu, Kenji Kise. A Novel Time-Division Multiplexing Approach for Emulation NoC Architectures on FPGAs, 情報処理学会第７７回全国大会, Mar. 2015.
• Thiem Van Thiem, Shimpei Sato, Kenji Kise. Challenge for Ultrafast 10K-Node NoC emulation on FPGA, 電子情報通信学会研究報告RECONF2014-21, pp. 23-28, Sept. 2014.
• Haruka Mori, Shimpei Sato, Chu Van Thiem, Kenji Kise. Design and Implementation of Manycore Processor for a Large FPGA, 情報処理学会第76回全国大会, Mar. 2014.

学位論文

• Hardware-Accelerated Modeling of Large-Scale Networks-on-Chip,  Summary,  Doctor (Engineering),  Tokyo Institute of Technology,  2018/09/20,   
• Hardware-Accelerated Modeling of Large-Scale Networks-on-Chip,  Exam Summary,  Doctor (Engineering),  Tokyo Institute of Technology,  2018/09/20,   
• Hardware-Accelerated Modeling of Large-Scale Networks-on-Chip,  Thesis,  Doctor (Engineering),  Tokyo Institute of Technology,  2018/09/20,   

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