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Publication List - YASUYUKI MIYAMOTO 2007 (14 / 477 entries)
Journal Paper
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Chia-Yuan Chang,
Heng-Tung Hsu,
Edward Yi Chang,
Chien-I Kuo,
Suman Datta,
Marko Radosavljevic,
YASUYUKI MIYAMOTO,
Guo-Wei Huang.
Investigation of Impact Ionization in InAs-Channel HEMT for High-Speed and Low-Power Applications,
IEEE Electron Dev. Lett.,
vol. 28,
no. 10,
pp. 856-858,
Oct. 2007.
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Kazuya Nishihori,
Yasuyuki Miyamoto.
Numerical Analysis of the Effect of P-Regions on the I-V Kink in GaAs MESFETs,
Trans. IECE of Japan,
vol. E90-C,
no. 8,
pp. 1643-1649,
Aug. 2007.
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Chia-Yuan Chang,
Edward Yi Chang,
Yi-Chung Lien,
Yasuyuki Miyamoto,
Chien-I Kuo,
Sze-Hung Chang,
Li-Hsin Chu.
High-PerformanceIn0.52Al0.48As/In0.6Ga0.4As Power Metamorphic High Electron Mobility Transistor for Ka-Band Applications,
Jpn. J. Appl. Phys.,
Vol. 46,
No. 6A,
pp. 3385-3387,
June 2007.
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Y. Miyamoto,
M. Ishida,
T. Yamamoto,
T. Miura,
K. Furuya.
InP buried growth of SiO2 wires toward reduction of collector capacitance in HBT,
J. Cryst, Growth,
Vol. 298,
pp. 867–870,
2007.
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A. Suwa,
I. Kashima,
Y. Miyamoto,
K. Furuya.
Increase of collector current in hot electron transistors controlled by gate bias,
Jpn. J. Appl. Phys.,,
Vol. 46,
No. 9,
pp. L202-L204,
2007.
International Conference (Reviewed)
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Shinnosuke Takahashi,
Tsukasa Miura,
Hiroaki Yamashita,
Yasuyuki Miyamoto,
Kazuhito Furuya.
DC Characteristics of Heterojunction Bipolar Transistor with Buried SiO2 Wires in Collector,
The 34th International Symposium on Compound Semiconductors,
Oct. 2007.
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Hiroaki Yamashita,
Tsukasa Miura,
Shinnosuke Takahashi,
YASUYUKI MIYAMOTO,
KAZUHITO FURUYA.
Fabrication of 200-nm-thick SiO2 wires buried in InP for reduction in collector capacitance in InP/InGaAs DHBT,
7th Topical Workshop on Heterostructure Microelectronics,
Aug. 2007.
Official location
International Conference (Not reviewed / Unknown)
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N. Kashio,
K. Kurishima,
Y. Fukai,
S. Yamahata,
Y. Miyamoto.
Emitter layer design for highly reliable and high-speed InP HBTs,
19th International Conference on Indium Phosphide and Related Materials (IPRM’07),
pp. PD1,
May 2007.
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T. Hino,
A. Suwa,
T. Hasegawa,
H. Saito,
M. Oono,
Y. Miyamoto,
K. Furuya.
Fabrication of hot electron transistors controlled by insulated gate,
19th International Conference on Indium Phosphide and Related Materials (IPRM'07),
pp. PA-11,
May 2007.
Domestic Conference (Not reviewed / Unknown)
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TOMOHIRO YAMADA,
KAZUHITO FURUYA,
YASUYUKI MIYAMOTO.
先端ノンドープ構造ホットエレクトロンエミッタ充電時間解析,
応用物理学会秋季,
4p-K-4,
Sept. 2007.
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日野高宏,
諏訪輝,
齋藤尚史,
宮本恭幸,
古屋一仁.
絶縁ゲートホットエレクトロントランジスタのエミッタ微細化,
応用物理学会関連連合講演会,
応用物理学会,
pp. 27p-X-4,
Mar. 2007.
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齋藤尚史,
諏訪輝,
長谷川貴史,
日野高宏,
大野真也,
五十嵐満彦,
宮本恭幸,
古屋一仁.
絶縁ゲートにより制御するホットエレクトロントランジスタの走行層幅微細化,
電気学会デバイス研究会,
電気学会デバイス研究会,
pp. EDD-07-42,
Mar. 2007.
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山下浩明,
三浦司,
高橋新之助,
宮本恭幸,
古屋一仁.
SiO2細線埋め込みHBTにおけるコレクタ容量削減のための200nm厚細線,
応用物理学会学術講演会,
応用物理学会,
pp. 27a-SM-8,,
Mar. 2007.
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高橋新之助,
三浦司,
山下浩明,
宮本恭幸,
古屋一仁.
コレクタ層内にSiO2細線を埋め込んだHBTのDC特性,
応用物理学会関連連合講演会,
応用物理学会,
pp. 27p-X-5,
Mar. 2007.
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