|
Publication List - Jaehoon Yu 2020 (7 / 28 entries)
Journal Paper
-
Ryutaro Doi,
Jaehoon Yu,
Masanori Hashimoto.
Sneak Path Free Reconfiguration with Minimized Programming Steps for Via-switch Crossbar Based FPGA,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
vol. 39,
no. 10,
pp. 2572-2587,
Oct. 2020.
-
TaiYu Cheng,
Yukata Masuda,
Jun Chen,
Jaehoon Yu,
Masanori Hashimoto.
Logarithm-approximate floating-point multiplier is applicable to power-efficient neural network training,
Vol. 74,
pp. 19-31,
May 2020.
International Conference (Reviewed)
-
Shungo Kumazawa,
Kazushi Kawamura,
Thiem Van Chu,
Masato Motomura,
Jaehoon Yu.
ExtraFerns: Fully Parallel Ensemble Learning Technique with Non-Greedy yet Minimal Memory Access Training,
International Symposium on Computing and Networking (CANDAR),
Nov. 2020.
-
Junnosuke Suzuki,
Kota Ando,
Kazutoshi Hirose,
Kazushi Kawamura,
Thiem Van Chu,
Masato Motomura,
Jaehoon Yu.
ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation,
International Symposium on Computing and Networking (CANDAR),
Nov. 2020.
-
Ángel López García-Arias,
Jaehoon Yu,
Masanori Hashimoto.
Low-Cost Reservoir Computing using Cellular Automata and Random Forests,
2020 IEEE International Symposium on Circuits and Systems (ISCAS),
pp. 1-5,
Oct. 2020.
-
Kazuki Onishi,
Jaehoon Yu,
Masanori Hashimoto.
Memory Efficient Training using Lookup-Table-based Quantization for Neural Network,
IEEE International Conference on Artificial Intelligence Circuits and Systems,
Sept. 2020.
-
M Hashimoto,
X Bai,
N Banno,
M Tada,
T Sakamoto,
J Yu,
R Doi,
Y Araki,
H Onodera,
T Imagawa,
H Ochi,
K Wakabayashi,
Y Mitsuyama,
T Sugibayashi.
Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications,
International Solid-State Circuits Conference,
pp. 502-503,
Feb. 2020.
[ Save as BibTeX ]
[ Paper, Presentations, Books, Others, Degrees: Save as CSV
]
[ Patents: Save as CSV
]
|