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Publication List - Shuichiro Yamamoto 2002 (9 / 220 entries)
Journal Paper
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山本修一郎,
石原宏.
FETのゲート容量を考慮した1T2C型強誘電体メモリの新規書込み法の提案と動作解析,
第49回応用物理学関係連合講演会講演予稿集,
Vol. 2,
pp. 544,
2002.
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Hiroshi Ishiwara,
Shuu'ichirou Yamamoto.
A novel data writing method in a 1T2C-type ferroelectric memory,
Facta Universitatis (Nis) - Elec. Energ.,
Vol. 15,
No. 1,
pp. 81-92,
2002.
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Shuu'ichirou Yamamoto,
Susumu Inoue,
Hiroshi Ishiwara.
Analysis of non-volatile latch circuits with ferroelectric-gate field effect transistors for low power and low voltage operation,
Proceedings of the 23rd International Conference on Microelectronics,
Vol. 2,
pp. 589-592,
2002.
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山本修一郎,
井上進,
石原宏.
不揮発性強誘電体ラッチ回路の新構成法と低電圧動作解析,
電子情報通信学会技術報告,
Vol. 101,
No. 719,
pp. 1-6,
2002.
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Shuu'ichirou Yamamoto,
Hyun-Soo Kim,
Hiroshi Ishiwara.
Proposal of a planar 8F2 1T2C-type ferroelectric memory cell,
Extended Abstract of the 2002 International Conference on Solid State Devices and Materials,
pp. 622-623,
2002.
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山本修一郎,
金■玄秀,
石原宏.
1T2C型強誘電体メモリアレイにおける書込み・読出しデータディスターブ低減法,
第63回応用物理学会学術講演会講演予稿集,
Vol. 2,
pp. 448,
2002.
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金■玄秀,
山本修一郎,
石原宏.
1T2C型強誘電体の高集積化とSPICEによる動作解析,
第63回応用物理学会学術講演会講演予稿集,
Vol. 2,
pp. 448,
2002.
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Hiroshi Ishiwara,
Shuu'ichirou Yamamoto.
A Novel Data Writing Method in a 1T2C-Type Ferroelectric Memory,
Proceedings of the 23rd International Conference on Microelectronics,
Vol. 2,
pp. 517-520,
2002.
Domestic Conference (Not reviewed / Unknown)
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加藤潤三,
MOTOSHI SAEKI,
大西淳,
永田守男,
Haruhiko Kaiya,
古宮誠一,
Shuichiro Yamamoto,
綿引健二,
蓬莱尚幸.
PAORE : パッケージ指向の要求獲得プロセス,
電子情報通信学会技術研究報告知能ソフトウェア工学KBSE2002-13~20,
Vol. 102,
No. 503,
pp. 25-30,
Dec. 2002.
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