論文

• Hiroyoshi Tanabe, Akira Jinguji, Atsushi Takahashi. Weakly guiding approximation of a three dimensional waveguide model for extreme ultraviolet lithography simulation, Journal of the Optical Society of America A, Optica Publishing Group, Vol. 41, Issue 8, pp. 1491-1499, July 2024.
• Hiroyoshi Tanabe, Akira Jinguji, Atsushi Takahashi. Accelerating extreme ultraviolet lithography simulation with weakly guiding approximation and source position dependent transmission cross coefficient formula, Journal of Micro/Nanopatterning, Materials, and Metrology, Vol. 23, Issue 1, 014201, Jan. 2024.
• Hiroyoshi Tanabe, Akira Jinguji, Atsushi Takahashi. Evaluation of convolutional neural network for fast extreme ultraviolet lithography simulation using imec 3 nm node mask patterns, Journal of Micro/Nanopatterning, Materials and Metrology (JM3), Society of Photo-optical Instrumentation Engineers, Vol. 22, Issue 2, 024201, June 2023.
• JINGUJI Akira, SATO Shimpei, NAKAHARA Hiroki. Weight Sparseness for a Feature-Map-Split-CNN Toward Low-Cost Embedded FPGAs, IEICE Transactions on Information and Systems, 一般社団法人 電子情報通信学会, Vol. E104.D, No. 12, pp. 2040-2047, Dec. 2021.
• Akira Jinguji, Shimpei Sato, Hiroki Nakahara. An FPGA Realization of a Random Forest with k-means Clustering using a High-level Synthesis Design, IEICE Transactions on Information and Systems, Vol. E101-D, No. 2, pp. 354-362, Feb. 2018.

国際会議発表 (査読有り)

• Hiroyoshi Tanabe, Akira Jinguji, Atsushi Takahashi. Pre-training CNN for fast EUV lithography simulation including M3D effects, Proc. SPIE 12954, DTCO and Computational Patterning III, 129540I, Society of Photo-Optical Instrumentation Engineers (SPIE), Apr. 2024.
• Hiroyoshi Tanabe, Akira Jinguji, Atsushi Takahashi. Accelerating EUV lithography simulation with weakly guiding approximation and STCC formula, Proc. SPIE 12750, International Conference on Extreme Ultraviolet Lithography 2023, 127500D, Society of Photo-Optical Instrumentation Engineers (SPIE), Nov. 2023.
• Hiroyoshi Tanabe, Akira Jinguji, Atsushi Takahashi. Evaluation of CNN for fast EUV lithography simulation using iN3 logic mask patterns, Proc. SPIE 12495, Advanced Lithography + Patterning 2023, 124951J, Apr. 2023.
• Hiroki Nakahara, Youki Sada, Masayuki Shimoda, Kouki Sayama, Akira Jinguji, Shimpei Sato. FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network, Sept. 2019.
• Hiroki Nakahara, Akira Jinguji, Masayuki Shimoda, Shimpei Sato. An FPGA-based Fine Tuning Accelerator for a Sparse CNN, The 27th International Symposium on Field-Programmable Gate Arrays (FPGA '19), pp. 186-186, Feb. 2019.
• Akira Jinguji, Tomoya Fujii, Shimpei Sato, Hiroki Nakahara. An FPGA Realization of OpenPose based on a Sparse Weight Convolutional Neural Network, The 2018 International Conference on Field-Programmable Technology (FPT '18), Dec. 2018.
• Hiroki Nakahara, Akira Jinguji, Shimpei Sato, Tsutomu Sasao. A Random Forest using a Multi-valued Decision Diagram on an FPGA, The 47th IEEE International Symposium on Multiple-valued Logic (ISMVL 2017), May 2017.
• Hiroki Nakahara, Akira Jinguji, Tomoya Fujii, Shimpei Sato. An Acceleration of a Random Forest Classification using Altera SDK for OpenCL, The International Conference on Field-Programmable Technology (FPT 2016), Dec. 2016.

国内会議発表 (査読有り)

• 山本 克治, 神宮司 明良, 高橋 篤司. MEDAバイオチップのための液滴運搬経路探索アルゴリズム, DAシンポジウム2023 論文集, pp. 173-179, Aug. 2023.  公式リンク  
  

国内会議発表 (査読なし・不明)

• 神宮司明良, 佐藤真平, 中原啓貴. Wide-SIMDを用いたISAベースのスパースCNNのFPGA実装, 電子情報通信学会技術研究報告, Vol. 119, No. 287, pp. 9-14, Nov. 2019.
• 神宮司明良, 佐藤真平, 中原啓貴. Feature-Map Separable Convolutionによる小メモリFPGAでの画像認識の実現, 電子情報通信学会技術研究報告, vol. 118, no. 340, pp. 39-44, Dec. 2018.
• 神宮司明良, 佐藤真平, 中原啓貴. 特徴空間の分割にk平均法を導入したランダムフォレストのFPGA実装, 第30回多値論理とその応用研究会, Jan. 2017.
• 中原啓貴, 神宮司明良, 佐藤真平, 笹尾勤, 丸山直也. 多値決定グラフを用いたランダムフォレストに関して, 第39回 多値論理フォーラム, Sept. 2016.

学位論文

• A Study on Design Optimization for FPGA-based Machine Learning Accelerator,  Thesis,  Doctor (Engineering),  Tokyo Institute of Technology,  2022/03/26,   
• A Study on Design Optimization for FPGA-based Machine Learning Accelerator,  Summary,  Doctor (Engineering),  Tokyo Institute of Technology,  2022/03/26,   
• A Study on Design Optimization for FPGA-based Machine Learning Accelerator,  Exam Summary,  Doctor (Engineering),  Tokyo Institute of Technology,  2022/03/26,   

[ BibTeX 形式で保存 ]    [ 論文・著書をCSV形式で保存 ]    [ 特許をCSV形式で保存 ]