Journal Paper

• Hiroyoshi Tanabe, Masayuki Shimoda, Atsushi Takahashi. Rigorous electromagnetic simulator for extreme ultraviolet lithography and convolutional neural network reproducing electromagnetic simulations, Journal of Micro/Nanopatterning, Materials and Metrology (JM3), Vol. 24, issue 2, May 2025.
• Zezhong Wang, Masayuki Shimoda, Atsushi Takahashi. SDG Channel Routing to Minimize Wirelength for Generalized Channel, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E108-A, No. 3, pp. 500-508, Mar. 2025.
• Masayuki Shimoda, Atsushi Takahashi. Gridless Gap Channel Routing with Variable-width Wires, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E108-A, No. 3, pp. 517-524, Mar. 2025.
• Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi, Mathieu Molongo, Makoto Minami, Katsuya Nishioka. A Fast Three-layer One-side Bottleneck Channel Routing with Layout Constraints using ILP, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E108-A, No. 3, pp. 509-516, Mar. 2025.
• Masayuki Shimoda, Atsushi Takahashi. Gridless Gap Channel Routing to Minimize Wirelength, IPSJ Trans. on System LSI Design Methodology, Vol. 18, pp. 2-9, Feb. 2025.  Official location  

International Conference (Not reviewed / Unknown)

• Hiroyoshi Tanabe, Atsushi Takahashi. Absorber dependence of M3D overlay errors in high-NA and hyper-NA EUV lithography, Advanced lithography + patterning, Proc. SPIE, SPIE, Vol. 13424, pp. 134240Q-1-6, Apr. 2025.

Domestic Conference (Not reviewed / Unknown)

• Yo Sakakura, Satoshi Tayu, Masayuki Shimoda, Atsushi Takahashi. A Note on 4-Layer U-shape Bottleneck Channel Routing, Technical Committee on VLSI Design Technologies, IEICE Technical Report (VLD2024-108), Vol. 124, No. 400, pp. 31-36, Mar. 2025.
• Emuun Purevdagva, Masayuki Shimoda, Satoshi Tayu, Atsushi Takahashi. Fast Droplet Routing Algorithm for MEDA-Based DMFB, Technical Committee on VLSI Design Technologies, IEICE Technical Report (VLD2024-105), Vol. 124, No. 400, pp. 13-18, Mar. 2025.
• Masaki Kuramochi, Yukihide Kohira, Atsushi Takahashi, Chikaaki Kodama. プロセスばらつきを考慮した交互最小化を用いたソースマスク最適化, Technical Committee on VLSI Design Technologies, IEICE Technical Report (VLD2024-83), Vol. 124, No. 329, pp. 41-46, Jan. 2025.
• Masayuki Shimoda, Atsushi Takahashi, Kosuke Yanagidaira, Mikiko Hirai, Toshikazu Watanabe, Toshimitsu Iwasawa, Chikaaki Kodama. Global Routing for CBA-based 3D Flash Memory, Technical Committee on VLSI Design Technologies, IEICE Technical Report (VLD2024-82), Vol. 124, No. 329, pp. 33-40, Jan. 2025.

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