Journal Paper

• Hiroyoshi Tanabe, Akira Jinguji, Atsushi Takahashi. Weakly guiding approximation of a three dimensional waveguide model for extreme ultraviolet lithography simulation, Journal of the Optical Society of America A, Optica Publishing Group, Vol. 41, Issue 8, pp. 1491-1499, July 2024.
• Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi, Mathieu Molongo, Makoto Minami, Katsuya Nishioka. Two-layer Bottleneck Channel Track Assignment for Analog VLSI, IPSJ Trans. on System LSI Design Methodology, Vol. 17, pp. 67-76, June 2024.  Official location  
• Hiroyoshi Tanabe, Akira Jinguji, Atsushi Takahashi. Accelerating extreme ultraviolet lithography simulation with weakly guiding approximation and source position dependent transmission cross coefficient formula, Journal of Micro/Nanopatterning, Materials, and Metrology, Vol. 23, Issue 1, 014201, Jan. 2024.

International Conference (Reviewed)

• Zezhong Wang, Masayuki Shimoda, Atsushi Takahashi. BCA Channel Routing to Minimize Wirelength for Generalized Channel Problem, Proc. IEEE International Symposium on Circuits and Systems (ISCAS '24), May 2024.
• Hiroyoshi Tanabe, Akira Jinguji, Atsushi Takahashi. Pre-training CNN for fast EUV lithography simulation including M3D effects, Proc. SPIE 12954, DTCO and Computational Patterning III, 129540I, Society of Photo-Optical Instrumentation Engineers (SPIE), Apr. 2024.
• Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi, Mathieu Molongo, Makoto Minami, Katsuya Nishioka. A Fast Three-layer Bottleneck Channel Track Assignment with Layout Constraints using ILP, Proc. the 25th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2024), pp. 50-55, Mar. 2024.  Official location  Official location  

Domestic Conference (Not reviewed / Unknown)

• Zezhong Wang, Masayuki Shimoda, Atsushi Takahashi. Single Trunk Routing Problem for Generalized Channel, Technical Committee on VLSI Design Technologies, IEICE Technical Report (VLD2023-104), Vol. 123, No. 390, pp. 30-35, Feb. 2024.
• Zuan Jiyo, Satoshi Tayu, Atsushi Takahashi, Mathieu Molongo, Makoto Minami, Katsuya Nishioka. A Template Routing Method Using SMT Solver for Double Via-Constrained Pair Symmetric Routing Problem, Technical Committee on VLSI Design Technologies, IEICE Technical Report (VLD2023-102), Vol. 123, No. 390, pp. 18-23, Feb. 2024.
• Kazuya Taniguchi, Satoshi Tayu, Atsushi TAKAHASHI, モロンゴ マチュー, Makoto Minami, 西岡克也. Three-layer Bottleneck Channel Track Assignment for Pins Placed on Opposite Sides, Technical Committee on VLSI Design Technologies, IEICE Technical Report (VLD2023-103), Vol. 123, No. 390, pp. 24-29, Feb. 2024.

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