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Publication List - Koh Yamanaga (14 entries)
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Journal Paper
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Koh Yamanaga,
Shuhei Amakawa,
Kazuya Masu,
Takashi Sato.
A Universal Equivalent Circuit Model for Ceramic Capacitors,
IEICE Transactions on Fundamentals of Electronics,
IEICE Transactions on Fundamentals of Electronics,
IEICE Transactions on Fundamentals of Electronics,
Vol. E93-C,
No. 3,
pp. 347-354,
Mar. 2010.
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Koh Yamanaga,
Takashi Sato,
Kazuya Masu.
2-Port Modeling Technique for Surface-Mount Passive Components Using Partial Inductance Concept,
IEICE Transactions on Fundamentals of Electronics,
IEICE Transactions on Fundamentals of Electronics,
Vol. E92-A,
No. 4,
pp. 976-982,
Apr. 2009.
International Conference (Reviewed)
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Shiho Hagiwara,
Koh Yamanaga,
Ryo Takahashi,
Kazuya Masu,
Takashi Sato.
Linear Time Calculation of State-Dependent Power Distribution Network Capacitance.,
International Symposium on Quality Electronic Design (ISQED),
International Symposium on Quality Electronic Design (ISQED),
International Symposium on Quality Electronic Design (ISQED),
pp. 75-80,
Mar. 2010.
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K. Yamanaga,
S. Amakawa,
T. Sato,
K. Masu.
Two-Dimentional Moment Method for Analyzing Current Distribution of a Ceramic Capacitor,
2009 International Symposium on Electromagnetic Comptibility, Kyoto,
2009 International Symposium on Electromagnetic Comptibility,
IEICE,
pp. 575-578,
July 2009.
Official location
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S. Amakawa,
K. Yamanaga,
H. Ito,
T. Sato,
N. Ishihara,
K. Masu.
S-parameter-based modal decomposition of multiconductor transmission lines and its application to de-embedding,
International Conference on Microelectronic Test Structures (ICMTS),
International Conference on Microelectronic Test Structures (ICMTS),
pp. 177-180,
Apr. 2009.
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Takashi Sato,
Koh Yamanaga,
Kazuya Masu.
Non-invasive direct probing for on-chip voltage measurement,
International SoC design conference (ISOCC),
International SoC design conference (ISOCC),
pp. 350-353,
Nov. 2008.
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Koh Yamanaga,
Takashi Sato,
Kazuya Masu.
Accurate parasitic inductance determination of a ceramic capacitor through 2-port measurements,
17th Conference on Electrical Performance of Electronic Packaging (EPEP),
17th Conference on Electrical Performance of Electronic Packaging (EPEP),
pp. 119-122,
Oct. 2008.
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Koh Yamanaga,
Takashi Sato,
Masu Kazuya.
On-chip differential and common mode voltage measurement using off-chip referenced twin probing,
12th SPI,
12th SPI,
pp. 331-336,
May 2008.
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Koh Yamanaga,
Takashi Sato,
Masu Kazuya.
Substrate-geometry aware 2-port modeling for surface-mount passive components,
Asia-Pacific EMC Week 2008,
Asia-Pacific EMC Week 2008,
pp. 246-249,
May 2008.
Domestic Conference (Reviewed)
Domestic Conference (Not reviewed / Unknown)
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Shiho Hagiwara,
Ryo Takahashi,
Koh Yamanaga,
Takashi Sato,
Kazuya Masu.
A Study on Power-supply Capacitance Model Considering State Dependency,
2009 年 電子情報通信学会総合大会,
2009 年 電子情報通信学会総合大会,
電子情報通信学会,
C-12-30,
Mar. 2009.
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Koh Yamanaga Ryo Takahashi Shiho Hagiwara Takashi Sato Kazuya Masu,
Ryo Takahashi,
Shiho Hagiwara,
Takashi Sato,
Kazuya Masu.
Calculation of State-Dependent Power-Distribution-Network Capacitance Based on Table Look Up,
2009 年 電子情報通信学会総合大会,
2009 年 電子情報通信学会総合大会,
電子情報通信学会,
C-12-31,
Mar. 2009.
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Ryo Takahashi,
Koh Yamanaga,
Takashi Sato,
Kazuya Masu.
CMOS論理回路における電源網容量の入力状態依存性についての検討,
電子情報通信学会ソサエティ大会,
電子情報通信学会ソサエティ大会,
C-12-42,
pp. 111,
Sept. 2008.
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Koh Yamanaga,
Takashi Sato,
Kazuya Masu.
測定系の侵襲性を定量化可能なオンチップ電源電圧変動の直接測定手法,
電子情報通信学会総合大会,
電子情報通信学会総合大会,
pp. C-12-37,
Mar. 2008.
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