Journal Paper

• Shuichiro Yamamoto, Shuto, Y., Sugahara, S.. Nonvolatile flip-flop based on pseudo-spin-transistor architecture and its nonvolatile power-gating applications for low-power CMOS logic, EPJ Applied Physics, Vol. 63, No. 1, 2013.

International Conference (Reviewed)

• Shuto, Y., Shuichiro Yamamoto, Sugahara, S.. FinFET-based pseudo-spin-transistor: Design and performance, 2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013, 2013.
• Nakane, R., Shuto, Y., Sukegawa, H., Wen, Z.C., Shuichiro Yamamoto, Mitani, S., Tanaka, M., Inomata, K., Sugahara, S.. Monolithic integration of pseudo-spin-MOSFETs using a custom CMOS chip fabricated through multi-project wafer service, European Solid-State Device Research Conference, pp. 272-275, 2013.

Other Publication

• 周藤 悠介, Shuichiro Yamamoto, 介川 裕章, Wen ZhenChao, 中根 了昌, 三谷 誠司, 田中 雅明, 猪俣 浩一郎, 菅原 聡. ナノCMOSデバイスを用いた擬似スピンMOSFETの設計と性能 (シリコン材料・デバイス・IEDM特集(先端CMOSデバイス・プロセス技術)), 電子情報通信学会技術研究報告 : 信学技報, 一般社団法人電子情報通信学会, Vol. 112, No. 421, pp. 43-46, Jan. 2013.

Patent

• SATOSHI SUGAHARA, Shuu'ichirou Yamamoto, Yusuke Shuto. 電子回路. Patent. Registered. 国立大学法人東京工業大学. 2009/03/27. 特願2009-078082. 2010/10/14. 特開2010-232959. 特許第5234547号. 2013/04/05 2013.
• Shuu'ichirou Yamamoto, SATOSHI SUGAHARA. スピン注入磁化反転ＭＴＪを用いた不揮発性ＳＲＡＭ／ラッチ回路. Patent. Registered. 国立大学法人東京工業大学. 2008/07/31. 特願2009-530030. 2010/11/25. 再表2009/028298. 特許第5170706号. 2013/01/11 2013.

[ Save as BibTeX ]    [ Paper, Presentations, Books, Others, Degrees: Save as CSV ]    [ Patents: Save as CSV ]