|
Publication List - Shuichiro Yamamoto 2016 (7 / 220 entries)
Journal Paper
-
Y. Takamura,
Y. Shuto,
S. Yamamoto,
H. Funakubo,
M. Kurosawa,
S. Nakagawa,
S. Sugahara.
Inverse-magnetostriction-induced switching current reduction of STT-MTJs and its application for low-voltage MRAM,
Solid-State Electron.,
vol. 128,
no. Supplement C,
pp. 194-199,
Oct. 2016.
Official location
Book
International Conference (Reviewed)
-
Y. Shuto,
S. Yamamoto,
S. Sugahara.
Energy Performance of Nonvolatile Power-Gating SRAM Using SOTB Technology,
46th European Solid-State Device Conference,
Sept. 2016.
-
Y. Shuto,
S. Yamamoto,
S. Sugahara.
Design and Implementation of Nonvolatile Power-Gating SRAM Using SOTB Technology,
International Symposium on Low Power Electronics and Design, San Francisco,
Aug. 2016.
-
Y. Shuto,
S. Yamamoto,
S. Sugahara.
Nonvolatile Power-gating Architecture for SRAM using SOTB Technology,
016 IEEE Silicon Nanoelectronics Workshop (SNW 2016),
June 2016.
-
Y. Shuto,
S. Yamamoto,
S. Sugahara.
New power-gating architectures using nonvolatile retention: Comparative study of nonvolatile power-gating (NVPG) and normally-off architectures for SRAM,
29th IEEE International Conference on Microelectronic Test Structures (ICMTS),
8-1,
Mar. 2016.
-
Y. Takamura,
Y. Shuto,
S. Yamamoto,
H. Funakubo,
M.K. Kurosawa,
S. Nakagawa,
S. Sugahara.
Inverse-magnetostriction-induced switching current reduction of STT-MTJs and its application for low-voltage MRAMs,
2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS),
2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS),
pp. 72-75,
Jan. 2016.
Official location
[ Save as BibTeX ]
[ Paper, Presentations, Books, Others, Degrees: Save as CSV
]
[ Patents: Save as CSV
]
|