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Publication List - Shuichiro Yamamoto 2014 (6 / 220 entries)
Journal Paper
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R. Nakane,
Y. Shuto,
H. Sukegawa,
Z.C. Wen,
S. Yamamoto,
S. Mitani,
M. Tanaka,
K. Inomata,
S. Sugahara.
Fabrication of pseudo-spin-MOSFETs using a multi-project wafer CMOS chip,
Solid-State Electronics,
Elsevier,
Vol. 102,
pp. 52-58,
Dec. 2014.
Book
International Conference (Reviewed)
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Yusuke Shuto,
Shuu'ichirou Yamamoto,
Satoshi Sugahara.
Comparative Study of Power-Gating Architectures for Nonvolatile SRAM Cells Based on Spintronics Technology,
2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS2014),
Nov. 2014.
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Yusuke Shuto,
Shuu'ichirou Yamamoto,
Satoshi Sugahara.
Near-threshold voltage operation of nonvolatile SRAM cell based on pseudo-spin-FinFET architecture,
2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S Conference 2014),
Oct. 2014.
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Yusuke Shuto,
Shuu'ichirou Yamamoto,
Satoshi Sugahara.
0.5V operation and performance of nonvolatile SRAM cell based on pseudo-spin-FinFET architecture,
2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2014),
Sept. 2014.
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Y. Shuto,
S. Yamamoto,
S. Sugahara.
Design and performance of nonvolatile SRAM cells based on pseudo-spin-FinFET architecture,
2014 IEEE Silicon Nanotechnology Workshop (SNW2014),
June 2014.
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