論文

• Hanli Liu, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, Kenichi Okada. A 265-µW Fractional-N Digital PLL with Seamless Automatic Switching Sub-sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS, IEEE Journal of Solid-State Circuits (JSSC), Vol. 54, No. 12, pp. 3478-3492, Dec. 2019.
• Jian Pang, Shotaro Maki, Seitaro Kawai, Noriaki Nagashima, Yuuki Seo, Masato Dome, Hisashi Kato, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Yuki Terashima, Hanli Liu, Teerachot Siriburanon, Tn Aravind, Nurul Fajri, Tohru Kaneko, Toru Yoshioka, Bangan Liu, Yun Wang, Rui Wu, Ning Li, Korkut Kaan Tokgoz, Masaya Miyahara, Atsushi Shirane, Kenichi Okada. A 50.1Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay with Calibration of LO Feed-Through and I/Q Imbalance, IEEE Journal of Solid-State Circuits (JSSC), Vol. 54, No. 5, pp. 1375-1390, May 2019.
• Hanli Liu, Teerachot Siriburanon, Kengo Nakata, Wei Deng, Ju Ho Son, Dae Young Lee, Kenichi Okada, Akira Matsuzawa. A 28-GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G Mobile Communications in 65nm CMOS, IEICE Transactions on Electronics, Vol. E101-C, No. 4, pp. 187-196, Apr. 2018.
• Rui Wu, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Kento Kimura, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shotaro Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Korkut Kaan Tokgoz, Teerachot Siriburanon, Bangan Liu, Yun Wang, Jian Pang, Ning Li, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa. 64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay, IEEE Journal of Solid-State Circuits, Nov. 2017.
• Kenichi Okada, Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng. A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using Digital Sub-Sampling Architecture, IEEE Journal of Solid-State Circuits, Vol. 51, No. 6, pp. 1385-1397, June 2016.
• Teerachot Siriburanon, Satoshi Kondo, Makihiko Katsuragi, Hanli Liu, Kento Kimura, Wei Deng, Kenichi Okada, Akira Matsuzawa. A Low-Power Low-Noise mm-Wave Sub-Sampling PLL using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE802.11ad, IEEE Journal of Solid-State Circuits, IEEE, Vol. 51, No. 5, pp. 1246-1260, May 2016.
• Teerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa. A Constant-Current-Controlled Class-C Voltage-Controlled Oscillator using Self-Adjusting Replica Bias Circuit, IEICE Transactions on Electronics, IEICE, Vol. E98-C, No. 6, pp. 471-479, June 2015.
• Ning Li, Kenichi Okada, Takeshi Inoue, Takuichi Hirano, Qinghong Bu, Tn Aravind, Teerachot Siriburanon, Hitoshi Sakane, Akira Matsuzawa. High-Q Inductors on Locally Semi-Insulated Si Substrate by Helium-3 Bombardment for RF CMOS Integrated Circuits, IEEE Transactions on Electron Devices, IEEE, Vol. 62, No. 4, pp. 1269-1275, Apr. 2015.
• Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa. A Fully Synthesizable All-digital PLL with Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-resolution Digital Varactor Using Gated Edge Injection Technique, IEEE Journal of Solid-State Circuits, Vol. 50, No. 1, pp. 68-80, Jan. 2015.
• Ahmed Musa, Wei Deng, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa. A Compact, Low Power and Low Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration, IEEE Journal of Solid-State Circuits, Vol. 49, No. 1, pp. 50-60, Jan. 2014.
• Wei Deng, Teerachot Siriburanon, Ahmed Musa, Kenichi Okada, Akira Matsuzawa. A Sub-harmonic Injection-locked Quadrature Frequency Synthesizer with Frequency Calibration Scheme for Millimeter-wave TDD Transceivers, IEEE Journal of Solid-State Circuits, Vol. 48, No. 7, pp. 1710-1720, July 2013.
• Teerachot Siriburanon, Takahiro Sato, Ahmed Musa, Wei Deng, Kenichi Okada, Akira Matsuzawa. A 20GHz Push-Push Voltage-Controlled Oscillator Using Second-Harmonic Peaking Technique for a 60GHz Frequency Synthesizer, IEICE Transactions on Electronics, Vol. E96-C, No. 6, pp. 804-812, June 2013.

著書

• Teerachot Siriburanon, Hanli Liu, Kenichi Okada, Akira Matsuzawa, Wei Deng, Satoshi Kondo, Makihiko Katsuragi, Kento Kimura. IoT and Low-Power Wireless: Circuits, Architectures, and Techniques, CRC Press, July 2018.
• Wei Deng, Teerachot Siriburanon, Ahmed Musa, Kenichi Okada, Akira Matsuzawa. Low Phase Noise Quadrature Frequency Synthesizer for 60 GHz Radios, CRC Press, pp. 491-514, Nov. 2014.

国際会議発表 (査読有り)

• Hanli Liu, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, Kenichi Okada. A 265-µW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS, IEEE International Solid-State Circuits Conference (ISSCC), pp. 256-257, Feb. 2019.
• Rui Wu, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Kento Kimura, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shotaro Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Korkut Kaan Tokgoz, Teerachot Siriburanon, Bangan Liu, Yun Wang, Jian Pang, Ning Li, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa. Ultra-High-Data-Rate 60-GHz CMOS Transceiver for Future Radio Access Network, IEEE International Conference on ASIC, Oct. 2017.
• Dongsheng Yang, Wei Deng, Bangan Liu, Tn Aravind, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa. An HDL-Synthesized Injection-Locked PLL Using LC-Based DCO for On-chip Clock Generation, IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC),, Jan. 2017.
• Hanli Liu, Ning Li, Tn Aravind, Teerachot Siriburanon, Takeshi Inoue, Hitoshi Sakane, Takuichi Hirano, Kenichi Okada, Akira Matsuz. A -194.0dBc/Hz FoM CMOS Tail-Filtering VCO Using Helium-3 Ion Irradiation Technique, IEEE MTT-S European Microwave Conference, Oct. 2016.
• Dongsheng Yang, Wei Deng, Yuki Terashima, Teerachot Siriburanon, Tn Aravind, Toru Yoshioka, Kenichi Okada, Akira Matsuzawa. An LC-VCO based Synthesizable Injection-Locked PLL with an FoM of -250.3dB, IEEE European Solid-State Circuits Conference (ESSCIRC), Sept. 2016.
• Rui Wu, Seitaro Kawai, Yuuki Seo, Nurul Fajri, Kento Kimura, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Teerachot Siriburanon, Shotaro Maki, Bangan Liu, Yun Wang, Noriaki Nagashima, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa. A 42Gb/s 60GHz CMOS Transceiver for IEEE802.11ay, IEEE International Solid-State Circuits Conference, Feb. 2016.
• Dongsheng Yang, Wei Deng, Tharayil Narayanan Aravind, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa. An Automatic Place-and-Routed Two-Stage Fractional-N Injection-locked PLL Using Soft Injection, IEEE ACM Asia South Pacific Design Automation Conference, Jan. 2016.
• Teerachot Siriburanon, Liu Hanli, Kengo Nakata, Wei Deng, Ju Ho Son, Dae Young Lee, Kenichi Okada, Akira Matsuzawa. A 28-GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G Cellular, IEEE European Solid-State Circuits Conference, Sept. 2015.
• Wei Deng, Dongsheng Yang, Tn Aravind, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa. A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique, IEEE International Solid-State Circuits Conference (ISSCC),, Feb. 2015.
• Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa. A 2.2-GHz -242dB-FoM 4.2-mW ADC-PLL Using Digital Sub-Sampling Architecture, IEEE International Solid-State Circuits Conference (ISSCC),, Feb. 2015.
• Teerachot Siriburanon, Tomohiro Ueno, Kento Kimura, Satoshi Kondo, Wei Deng, Kenichi Okada, Akira Matsuzawa. A 58.3-to-65.4GHz 34.2mW Sub-Harmonically Injection-Locked PLL with a Sub-Sampling Phase Detection,, IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC), Jan. 2015.
• Dongsheng Yang, Wei Deng, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa. An HDL-Synthesized Gated-Edge-Injection PLL with A Current Output DAC, IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC), Jan. 2015.
• Ning Li, Kenichi Okada, Takeshi Inoue, Takuichi Hirano, Qinghong Bu, Aravind Tharayil Narayanan, Teerachot Siriburanon, Hitoshi Sakane, Akira Matsuzawa. High-Q Inductors on Locally Semi-Insulated Si Substrate by Helium-3 Bombardment for RF CMOS Integrated Circuits, IEEE Symposium on VLSI Technology (VLSI Technology), pp. 189-190, June 2014.
• Teerachot Siriburanon, Tomohiro Ueno, Kento Kimura, Satoshi Kondo, Wei Deng, Kenichi Okada, Akira Matsuzawa. A 60-GHz Sub-Sampling Frequency Synthesizer Using Sub-Harmonic Injection-Locked Quadrature Oscillators, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June 2014.
• Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa. A 0.0066-mm2 780-µW Fully Synthesizable PLL with a Current Output DAC and an Interpolative-Phase Coupled Oscillator using Edge Injection Technique, IEEE International Solid-State Circuits Conference (ISSCC), pp. 266-267, Feb. 2014.
• Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa. A Dual-loop Injection-locked PLL with All-digital Background Calibration System for On-chip Clock Generation, IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC), pp. 21-22, Jan. 2014.
• Teerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa. A Swing-Enhanced Current-Reuse Class-C VCO with Dynamic Bias Control Circuits, IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC), pp. 25-26, Jan. 2014.
• .Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa. A Dual-Step-Mixing ILFD using a Direct Injection Technique for High-Order Division Ratios in 60GHz Applications, IEICE Thailand-Japan MicroWave (TJMW), Dec. 2013.
• Teerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa. A Constant-Current-Controlled Class-C VCO using a Self-Adjusting Replica Biasing Scheme, IEEE MTT-S European Microwave Conference, Oct. 2013.
• Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa. A 13.2% Locking-Range Divide-by-6, 3.1mW, ILFD Using Even-Harmonic-Enhanced Direct Injection Technique for Millimeter-Wave PLLs, IEEE European Solid-State Circuits Conference, Sept. 2013.
• Teerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa. A Current-Reuse Class-C LC-VCO with an Adaptive Bias Scheme,, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June 2013.
• Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa. A 60GHz PVT-Tolerant Injection-locked Frequency Synthesizer with a Background Calibration Technique, IEEE EDS WIMNACT-37 Future Trend of Nanodevices and Photonics,, Feb. 2013.
• Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa. A 0.022mm2 970µW Injection-Locked PLL with -243dB FOM using Synthesizable All-Digital PVT Calibration Circuits, IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2013.
• Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa. A Sub-harmonic Injection-locked Frequency Synthesizer with Frequency Calibration Scheme for Use in 60GHz TDD Transceivers, IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC), Jan. 2013.
• Wei Deng, Teerachot Siriburanon, Ahmed Musa, Kenichi Okada, Akira Matsuzawa. A Fractional-N Harmonic Injection-locked Frequency Synthesizer with 10MHz-6.6GHz Quadrature Outputs for Software-Defined Radios, IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC),, Jan. 2013.
• Teerachot Siriburanon, Takahiro Sato, Ahmed Musa, Wei Deng, Kenichi Okada, Akira Matsuzawa. A 20 GHz Push-Push Voltage-Controlled Oscillator for a 60 GHz Frequency Synthesizer, IEEE Asia-Pacific Microwave Conference (APMC), Dec. 2012.
• Wei Deng, Teerachot Siriburanon, Ahmed Musa, Kenichi Okada, Akira Matsuzawa. "A 58.1-to-65.0GHz Frequency Synthesizer with Background Calibration for Millimeter-wave TDD Transceivers,", IEEE European Solid-State Circuits Conference (ESSCIRC), Sept. 2012.

国際会議発表 (査読なし・不明)

• Teerachot Siriburanon, Tomohiro Ueno, Kento Kimura, Satoshi Kondo, Wei Deng, Kenichi Okada, Akira Matsuzawa. A 60-GHz Sub-Sampling PLL Using A Dual-Step-Mixing ILFD,(invited), IEEE Asia-Pacific Microwave Conference (APMC), Nov. 2014.

国内会議発表 (査読なし・不明)

• Dingxin Xu, Hanli Liu, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, 染谷 晃基, 白根 篤史, 岡田 健一. A 265-µW Fractional-N Digital PLL with Switching Subsampling/Sampling Feedback, 電子情報通信学会 LSIとシステムのワークショップ, May 2019.
• Hanli Liu, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Pang Jian, Yun Wang, Rui Wu, 染谷 晃基, Atsushi Shirane, Kenichi Okada. A 265-µW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS, IEEE SSCS Japan Chapter ISSCC報告会, Mar. 2019.
• Hanli Liu, Teerachot Siriburanon, Kengo Nakata, Wei Deng, Kenichi Okada, Akira Matsuzawa. A 28GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G New Radio, 電子情報通信学会 集積回路研究会, Vol. ICD2017-89, pp. 147-150, Dec. 2017.
• Jian Pang, 眞木 翔太郎, 河合 誠太郎, 永島 典明, 瀬尾 有輝, 桂木 真希彦, 木村 健将, 近藤 智史, Hanli Liu, Teerachot Siriburanon, 金子 徹, 宮原 正也, 岡田 健一, 松澤 昭. A 128-QAM 60GHz CMOS Transceiver for IEEE802.11ay with Calibration of LO Feedthrough and I/Q Imbalance, 電子情報通信学会 LSIとシステムのワークショップ, May 2017.
• Jian Pang, 眞木 翔太郎, 河合 誠太郎, 永島 典明, 瀬尾 有輝, 桂木 真希彦, 木村 健将, 近藤 智史, Hanli Liu, Teerachot Siriburanon, 岡田 健一, 松澤 昭. 「IEEE802.11ayに向けたCMOS ミリ波トランシーバーに関する研究, 電子情報通信学会集積回路研究会, Vol. ICD2016-13, pp. 113-118, Mar. 2017.
• Dongsheng Yang, Wei Deng, 中田 憲吾, Teerachot Siriburanon, 岡田 健一, 松澤 昭. A Fully Synthesized Fractional-N IL-PLL Using Only Digital Library, 電子情報通信学会 総合大会, C-12-9, Mar. 2016.
• ｳｰ ﾙｲ, 河合 誠太郎, 瀬尾 有輝, NURUL FAJRI, 木村 健将, 佐藤 慎司, 近藤 智史, 上野 智大, SIRIBURANON T, 真木翔太郎, Liu Bangan, Wang Yun, 永島 典明, 宮原 正也, 岡田 健一, 松澤 昭. A 42Gb/s 60GHz CMOS Transceiver for IEEE802.11ay, IEEE SSCS Japan Chapter ISSCC報告会, Feb. 2016.
• Hanli Liu, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa. 28GHz CMOS LC-VCO Using Frequency Doubling Technique, 電子情報通信学会 ソサイエティ大会, Sept. 2015.
• 中田 憲吾, Wei Deng, Dongsheng Yang, 上野 智大, THARAYILNAARAVIND, Teerachot Siriburanon, 近藤 智史, 岡田 健一, 松澤 昭. 注入同期を利用した自動合成配置配線可能なAll Digital Synthesizable PLL, 電子情報通信学会 LSIとシステムのワークショップ, May 2015.
• Teerachot Siriburanon, 近藤 智史, 木村 健将, 上野 智大, 川嶋 理史, 金子 徹, Wei Deng, 宮原 正也, 岡田 健一, 松澤 昭. A Digital Sub-sampling ADC-PLL with -112dBc/Hz In-band Phase Noise and 380fsrms Jitter, 電子情報通信学会 アナログRF研究会, Mar. 2015.
• .Wei Deng, Dongsheng Yang, Aravind Tharayil Narayanan,, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa. A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique, IEEE SSCS Kansai Chapter ISSCC報告会, Mar. 2015.
• 寺嶋 友樹, Teerachot Siriburanon, 岡田 健一, 松澤 昭. 2.25分周器に関する検討, 電子情報通信学会 ソサイエティ大会, C-12-17, Sept. 2014.
• ning li, Kenichi Okada, Takeshi Inoue, Takuichi Hirano, Qinghong Bu, Aravind Tharayil Narayanan, Teerachot Siriburanon, Hotoshi Sakane, Akira Matsuzawa. High-Q Inductors on Locally Semi-Insulated Si Substrate by Helium-3 Bombardment for RF CMOS Integrated Circuits, 応用物理学会 シリコンテクノロジー分科会, Aug. 2014.
• 桂木 真希彦, 上野 智大, Teerachot Siriburanon, 木村 健将, 近藤 智史, 岡田 健一, 松澤 昭. ミリ波64QAM通信を実現する60GHz帯局部発振器, 電子情報通信学会 LSIとシステムのワークショップ, May 2014.
• Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa. A 0.0066mm2 780µW Fully Synthesizable PLL with a Current Output DAC and an Interpolative-Phase Coupled Oscillator using Edge Injection Technique, IEEE SSCS Japan Chapter ISSCC報告会, May 2014.
• Dongsheng Yang, Wei Deng, Teerachot Siriburanon, 岡田 健一, 松澤 昭. A 0.4ps/bit Digitally-controlled Varactor for a Fully Synthesizable DCO, 電子情報通信学会 総合大会, C-12-36, Mar. 2014.
• Teerachot Siriburanon, Wei Deng, Ahmed Magdi Hassan Musa, Kenichi Okada, Akira Matsuzawa. A Dual-Step-Mixing ILFD using a Direct Injection Technique for High-Order Division Ratios in 60GHz Applications, 電子情報通信学会 総合大会, CI-1-3, Mar. 2014.
• Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa. Digitally Synthesized PLL with a DAC and Phase-Coupled Oscillator using Standard Cells Only, 電子情報通信学会 総合大会, C-12-30, Mar. 2014.
• Teerachot Siriburanon, Wei Deng, Ahmed Musa, 岡田 健一, 松澤 昭. A Divide-by-4 and Divide-by-6 Injection-locked Frequency Divider using Even-Harmonic Direct Injection Method for V-band Applications, 電子情報通信学会 アナログRF研究会, Vol. RF2013-2, p. 1, Nov. 2013.
• Teerachot Siriburanon, Wei Deng, 岡田 健一, 松澤 昭. A Current-Reuse Class-C VCO using Dynamic Start-up Circuits, 電子情報通信学会 ソサイエティ大会, 電子情報通信学会ソサイエティ大会講演論文集, C-12-32, Sept. 2013.
• Wei Deng, Ahmed Musa, Teerachot Siriburanon, 宮原 正也, 岡田 健一, 松澤 昭. A Dual-Loop Injection-Locked PLL with All-Digital PVT Calibration System, 電子情報通信学会 総合大会, C-12-58, Mar. 2013.
• Wei Deng, Ahmed Musa, Teerachot Siriburanon, 宮原 正也, 岡田 健一, 松澤 昭. A PVT-tolerant Dual-loop Injection-locked PLL for Clock Generation, 電子情報通信学会 シリコンアナログRF研究会, Vol. RF2012-4, p. 4, Mar. 2013.
• Wei Deng, Ahmed Musa, Teerachot Siriburanon, 宮原 正也, 岡田 健一, 松澤 昭. A 0.022mm2 970µW Injection-Locked PLL with -243dB FOM using Synthesizable All-Digital PVT Calibration Circuits, IEEE SSCS 関西 Chapter ISSCC報告会, Mar. 2013.
• Teerachot Siriburanon, 岡田 健一, 松澤 昭. A 60GHz Frequency Synthesizer Using a PVT-Tolerant Subharmonic Injection Technique, STARCシンポジウム, p. 12, Jan. 2013.
• Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa. A 60GHz PVT-tolerant Injection-locked Frequency Synthesizer with a Background Frequency Calibration Technique, 電子情報通信学会 シリコンアナログRF研究会, Vol. RF2012-3, p. 7, Dec. 2012.
• Teerachot Siriburanon, Takahiro Sato, Ahmed Musa, Wei Deng, Kenichi Okada, Akira Matsuzawa. A 20GHz Push-Push Voltage-Controlled Oscillator for a MM-Wave Frequency Synthesizer, 電子情報通信学会 ソサイエティ大会, C-12-15, Sept. 2012.
• Teerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa. A Wide Frequency Range 60GHz Static Frequency Divider Using Shunt-Series Peaking, 電子情報通信学会 ソサイエティ大会, C-12-33, Sept. 2011.

学位論文

• Low-Power and Low-Jitter Frequency Synthesizers for High-Speed Wireless Communications,  Summary,  Doctor (Academic),  Tokyo Institute of Technology,  2016/03/26,   
• Low-Power and Low-Jitter Frequency Synthesizers for High-Speed Wireless Communications,  Exam Summary,  Doctor (Academic),  Tokyo Institute of Technology,  2016/03/26,   
• Low-Power and Low-Jitter Frequency Synthesizers for High-Speed Wireless Communications,  Thesis,  Doctor (Academic),  Tokyo Institute of Technology,  2016/03/26, 
• 高速無線通信に向けた低消費電力かつ低ジッタ周波数シンセサイザの研究,  要約,  博士(学術),  東京工業大学,  2016/03/26,   

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