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Publication List - YASUYUKI MIYAMOTO 2011 (26 / 477 entries)
Journal Paper
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N. Takebe,
T. Kobayashi,
H. Suzuki,
Y. Miyamoto,
K. Furuya.
Fabrication of InP/InGaAs DHBTs with buried SiO2 wires,
IEICE Trans. Electron.,
IEICE,
vol. E94-C,
no. 5,
pp. 830-834,
May 2011.
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R. Terao,
T. Kanazawa,
S. Ikeda,
Y. Yonai,
A. Kato,
Y. Miyamoto.
InP/InGaAs Composite MOSFETs with Regrown Source and Al2O3 gate dielectric Exhibiting Maximum Drain Current Exceeding 1.3 mA/μm,
Applied Phys. Exp.,
The Japan Society of Applied Physics,
vol. 4,
no. 5,
054201,
Apr. 2011.
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M. Yamada,
T. Uesawa,
Y. Miyamoto,
K. Furuya.
Deviation from Proportional Relationship between Emitter Charging Time and Inverse Current of Heterojunction Bipolar Transistors Operating at High Current Density,
IEEE Electron Device Lett.,
IEEE,
vol. 32,
# 4,
pp. 491-493,
Apr. 2011.
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H. Saito,
Y. Matsumoto,
Y. Miyamoto,
K. Furuya.
Vertical InGaAs Channel Metal–Insulator–Semiconductor Field Effect Transistor with High Current Density,
Jpn. J. Appl. Phys.,
vol. 50,
no. 1,
014102,
Jan. 2011.
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Wang,
C.-T.,
Kuo,
C.-I.,
Hsu,
H.-T.,
Chang, E.Y.,
Hsu,
L.-H.,
Lim,
W.-C.,
YASUYUKI MIYAMOTO.
Flip-chip packaging of low-noise metamorphic high electron mobility transistors on low-cost organic substrate,
Japanese Journal of Applied Physics,
Vol. 50,
No. 9 PART 1,
2011.
Book
International Conference (Reviewed)
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YASUYUKI MIYAMOTO,
Hisashi Saito,
Toru Kanazawa.
High-current-density InP ultrafine devices for high-speed operation,
The International Conference on Infrared, Millimeter, and Terahertz Waves (IRMMW-THz),
Oct. 2011.
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T. Kanazawa,
R. Terao,
S. Ikeda,
Y. Miyamoto.
MOVPE-regrown source/drain regions for III-V MOSFETs with high drain current of 1.28 A/mm,
23rd Int. Conf. Indium Phosphide and Related Materials (IPRM2011),
Sept. 2011.
Official location
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N. Takebe,
Y. Miyamoto.
Reduction of Base-Collector Capacitance in InP/InGaAs DHBT with Buried SiO2 Wires,
2011 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices(AWAD),
Sept. 2011.
Official location
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A. Kato,
T. Kanazawa,
S. Ikeda,
Y. Yonai,
YASUYUKI MIYAMOTO.
Reduction of Access Resistance of InP/InGaAs Composite-Channel MOSFET with A Back Source Electrode,
2011 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices(AWAD),
Sept. 2011.
Official location
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Y. Yamaguchi,
T. Sagai,
Y. Miyamoto.
Fabrication of InP/InGaAs SHBT on Si Substrate by Using Transferred Substrate Process,
9th Topical Workshop on Heterostructure Materials,
Sept. 2011.
Official location
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Yosiharu Yonai,
Toru Kanazawa,
Shunsuke Ikeda,
YASUYUKI MIYAMOTO.
High Drain Current (>2A/mm) InGaAs channel MOSFET at VD=0.5V with Shrinkage of Channel Length by InP Anisotropic Etching,
2011 IEEE International Electron Devices Meeting (IEDM 2011),
2011.
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Matsumoto, Y.,
Saito, H.,
YASUYUKI MIYAMOTO.
Reduction of source parasitic capacitance in vertical InGaAs MISFET,
Conference Proceedings - International Conference on Indium Phosphide and Related Materials,
2011.
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Motohiko Fujimatsu,
Hisashi Saito,
YASUYUKI MIYAMOTO.
GaAsSb/InGaAs vertical tunnel FET with a 25 nm-wide channel mesa structure,
2011 International Conference on Solid State Devices and Materials(SSDM 2011),
2011.
Domestic Conference (Not reviewed / Unknown)
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YASUYUKI MIYAMOTO,
Yosiharu Yonai,
Toru Kanazawa.
InGaAs MOSFETの高電流密度化,
電子情報通信学会 電子デバイス研究会(ED),
Dec. 2011.
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YASUYUKI MIYAMOTO,
Toru Kanazawa.
InP系化合物半導体を用いたMOSFETの技術動向,
電気学会 電子・情報・システム部門大会,
Sept. 2011.
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Motohiko Fujimatsu,
Hisashi Saito,
YASUYUKI MIYAMOTO.
GaAsSb/InGaAsヘテロ接合を用いた縦型トンネルFETの作製・評価,
電子情報通信学会2011年ソサイエティ大会,
Sept. 2011.
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Atsushi Kato,
Toru Kanazawa,
YASUYUKI MIYAMOTO.
ソース裏面電極によるInP/InGaAsコンポジットチャネルMOSFETのアクセス抵抗低減,
電子情報通信学会2011年ソサイエティ大会,
Sept. 2011.
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Shunsuke Ikeda,
Toru Kanazawa,
YASUYUKI MIYAMOTO.
電子ランチャを持つInGaAs MOSFETにおけるヘテロ障壁高さ依存性,
電子情報通信学会2011年ソサイエティ大会,
Sept. 2011.
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大石 敏之,
大塚 浩志,
山中 宏治,
中山 正敏,
平野 嘉仁,
YASUYUKI MIYAMOTO.
C-10-7 緑色光照射時の等価回路パラメータ測定によるGaN HEMTのトラップ解析(C-10.電子デバイス,一般セッション),
電子情報通信学会ソサイエティ大会講演論文集,
一般社団法人電子情報通信学会,
Vol. 2011,
No. 2,
pp. 61,
Aug. 2011.
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Yuutarou Yamaguchi,
Takeru Sagai,
YASUYUKI MIYAMOTO.
基板転写プロセスを用いたSi基板上InP/InGaAs SHBTの作製,
第58回応用物理学会関係連合講演会,
Apr. 2011.
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Naoaki Takebe,
YASUYUKI MIYAMOTO.
InP/InGaAs DHBT におけるSiO2細線埋め込みによるベースコレクタ間容量の削減,
第58回応用物理学会関係連合講演会,
Apr. 2011.
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Yutaka Matsumoto,
Hisashi Saito,
YASUYUKI MIYAMOTO.
縦型InGaAs MIS-FETのソース寄生容量の削減,
電気学会電子デバイス研究会,
Mar. 2011.
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Motohiko Fujimatsu,
Hisashi Saito,
Tomoki Kususaki,
Yutaka Matsumoto,
Jun Hirai,
YASUYUKI MIYAMOTO.
GaAsSb/InGaAsヘテロ接合を用いた縦型トンネルFETに関する研究,
第58回応用物理学会関係連合講演会,
Mar. 2011.
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Toru Kanazawa,
Ryousuke Terao,
Yuutarou Yamaguchi,
Shunsuke Ikeda,
Yosiharu Yonai,
atsushi kato,
YASUYUKI MIYAMOTO.
裏面電極を有するⅢ-Ⅴ族量子井戸型チャネルMOSFET,
電子情報通信学会電子デバイス研究会,
Jan. 2011.
Patent
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