論文

• S. Nakajima, S. Nakamura, T. Ueki, T. Sakai. Sample preparation techniques for physical analysis of VLSIs, Microelectronics Reliability, Vol. 44, pp. 449-458, 2004.
• G. Yamanaka, S. Ohmi, T. Sakai. AlON thin films formed by ECR plasma oxidation for high-k gate insulator application, Mat. Res. Soc. Symp. Proc., Vol. 786, pp. E6.10.1-6, 2004.
• 大理洋征龍, 山崎崇, 盛田伸也, 袴田佳孝, 大見俊一郎, 酒井徹志. 極薄SOI層と素子間分離領域の形成を一体化する新技術：SBSI(Separation by Bonding Si Islands) -Si島とSi基板間の熱酸化-, 第65回応用物理学会学術講演会講演予稿集, pp. 745/Ⅱ, 2004.
• T. Kurose, T. Uchikawa, S. Ohmi, T. Sakai. HfOxNy Thin Films Formed by ECR Ar/N2 Plasma Oxidation of HfN Thin Films, The 15th Symposium of The Materials Research Society of Japan, pp. G1-O07-M,129, 2004.
• S. Ohmi, H. Ohri, T. Yamazaki, M. Sakuraba, J. Murota, T. Sakai. Novel SOI Fabrication Process Utilizing the Selective Etching for Si/Ge Stacked Layers: Separation By Bonding Si Islands Technology(SBSI), Third Internatinal Workshop on New Group Ⅳ (Si-Ge-C) Semiconductors: Control of Properties and Applications to Ultrahigh Speed and Opto-Electronic Devices, pp. 77-78, 2004.
• T. Sakai, T. Yamazaki, S. Ohmi, S. Morita, H. Ohri, J. Murota, M. Sakuraba, H. Omi, Y. Takahashi. Separation by Bonding Si Islands (SBSI) for LSI Applications, International SiGe Technology and Device Meeting(ISTDM 2004), pp. 230-231, 2004.
• H. Ohri, T. Yamazaki, S. Ohmi, T. Sakai. A Study on Selective Etching of SiGe Layers and Electrical Characteristics of MOS Diodes Formed after Selective Etching in SBSI Process, Third Internatinal Workshop on New Group Ⅳ (Si-Ge-C) Semiconductors: Control of Properties and Applications to Ultrahigh Speed and Opto-Electronic Devices, pp. 79-80, 2004.
• T. Yamazaki, S. Ohmi, S. Morita, H. Ohri, J. Murota, M. Sakuraba, H. Omi, T. Sakai. Separation by Bonding Si Islands for Advanced CMOS LSIs, Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices, pp. 77-78, 2004.
• T. Yamazaki, T. Sekikawa, S. Morita, Y. Hakamada, H. Ohri, S. Ohmi, T. Sakai. A Study on Selective Etching of SiGe Layers in SiGe/Si Systems for Device Applications, Mat. Res. Soc. Symp. Proc., Vol. 795, pp. U11.8.1-6, 2004.
• D. Sasaki, S. Ohmi, M. Sakuraba, J. Murota, T. Sakai. Proposal of a Multi-layer channel MOSFET: the application of selective etching for Si/SiGe stacked layers, Applied Surface Science, Vol. 224, pp. 270-273, 2004.
• Tetsushi Sakai, S. Ohmi, D. Sasaki, M. Sakuraba, J. Murota. A Proposal of Multi-Layer Channel MOSFET:The Application of Selective Etching for Si/Ge Stacked Layers, Abstracts of First Internatinal SiGe Technology and Device Meeting(ISTDM), pp. 31-32, 2003.
• S. Nakajima, S. Nakamura, K. Kuji, T. Ueki, T. Ajioka, T. Sakai. Construction of a cost-effective failure analysis service network microelectronics failure analysis service in Japan, Microelectronics Reliability, Vol. 42, pp. 511-521, 2002.
• T.Yamazaki, S.Ohmi, M. Sakuraba, J. Murota, T. Sakai. Double-Polysilicon self-aligned HBT with non-selective epitaxial SiGe:C base layer, Second International Workshop on New Group Ⅳ(Si‐Ge‐C)Semiconductors: Control of Properties and Applications to Ultra-high Speed and Opto‐Electronics Devices, Vol. June 2-4, No. (Yamanashi), pp. Ⅷ-006, 2002.
• 酒井徹志. 超高速Si系デバイスの現状と今後の展望, 日本学術振興会将来加工技術第１３６委員会合同研究会資料, pp. 33-38, 2000.
• 酒井徹志. 超低エネルギーデバイス（特にSOIデバイス）の現状と展望, RCJ信頼性シンポジウム予稿集, Vol. 10, pp. 1-6, 2000.
• Satoshi Nakayama, Tetsushi Sakai. The Effect of Nitorogen in a P+ Polysilicon Gate on Boron Penetration through the Gate Oxide, Journal Electrochemical Society, Vol. 144, No. 12, pp. 4326-4330, 1997.
• s.Nakashima, T. Ohono, S. Nakamura, T. Ueki, T. Tsuchiya, T. Takeda, Tetsushi Sakai. Sacrificial Oxidation Techniques of Top Si Layer to Reduce Source-to-Drein Leakage Current in 0.25-μm MOSFETs/SIMOX , proceedings 1996 IEEE International SOI Conference, pp. 124-125, 1996.
• M. Ino, H. Sawada, K. Nishimura, T. Takeda, Y. Kado, H. Inokawa, T. Tsuchiya, Y. Sakakibara, K. Izumi, Tetsushi Sakai. 0.25um CMOS/SIMOX Gate Array LSI, ISSCC Dig. Tech. Papers, pp. 86-87, 1996.
• Satoshi Nakayama, Tetsushi Sakai. Redistribution of in situ doped or Ion-implanted Nitorogen in Polysilicon, Journal Applied Physics, Vol. 79, No. 8, pp. 4024-4028, 1996.
• Satoshi Nakayama, Tetsushi Sakai. The Effect of Nitorogen in P+ Polysilicon Gates on Boron Penetration into Silicon Substrate through the Gate Oxide, Symposium on VLSI Tech. Dig. Tech. Papers, pp. 223-229, 1996.
• M. Urajin, J. Kodate, Y. Kobayashi, S. Konaka, Tetsushi Sakai. Very-High fT and fmax Silicon Bipolar Transistors using Ultra-High Performance Super Self-Aligned Process Technology for Low-Energy and Ultra-High Speed LSI's, International Electron Devices Meeting, pp. 735-738, 1995.
• Y. Kado, H. Inokawa, Y. Okazaki, T. Tsuchiya, Y. Kawai, M. Sato, Y. Sakakibara, M. Ino, T. Takeya, Tetsushi Sakai . Substantial Advantages of Fully-depleted CMOS/SIMOX Devices as Low-power High-Performance VLSI Components with its Bulk-CMOS Counterpart, International Electron Devices Meeting, pp. 635-639, 1995.
• Y. Kado, H. Inokawa, K. Nishimura, Y. Okazaki, M. Sato, T. Ohno, T. Tsuchiya, M. Ino, K. Takeya, Tetsushi Sakai. Comparison oy 1/4-micron-gate Fully-depleted CMOS/SIMOX and Bulk Gate Arrays for Low-Voltage, Low-power Applications, Extended Abstracts of the 27th Conference on Solid State Devices, pp. 572-574, 1995.
• Tetsushi Sakai. Present Status and Prospects of SR Lithography (it's application to Sub- and Deep Sub-quartermicron LSI's) (invite), The 6th International Micro process Coference, pp. 4-5, 1993.
• M. Fujishima, M. Yamashita, M. Ikeda, K. Asada, Y. Omura, K. Izumi, Tetsushi Sakai, T. Sugano. 1GHz 50uw 1/2 Frequency Divider Fabricated on Ultra-thin SIMOX Substrate, Symposium on VLSI Circuits Dig. Tech. Papers, pp. 46-47, 1992.
• H. Miki, T. Ohmameda, M. Kumon, K. Asada, T. Sugano, Y. Omura, K. Izumi, Tetsushi Sakai. Subfemutojoule Deep Submicrometer-Gate CMOS Built in Ultra-thin Si Film on SIMOX Substrates, IEEE Transaction on Electron Devices, Vol. 38, No. 2, pp. 373-377, 1991.
• S. Konaka, T. Kobayashi, T. Matsuda, M. Ugajin, K. Imai, Tetsushi Sakai. HSST/BiCMOS Technology with 26ps ECL and 45ps 2V CMOS Inverter, International Electron Devices Meeting, pp. 493-496, 1990.
• Y. Kobayashi, S. Nakayama, N. Shimoyama, Y. Tanabe, K. Miura, S. Nakajima, K. Izumi, Tetsushi Sakai. SST-BiCMOS Technology with 130ps CMOS and 50ps ECL, Symposium on VLSI Tech. Dig. Tech. Papers, pp. 85-86, 1990.
• S. Konaka, E. Yamamoto, K. Sakuma, Y. Amemiya, Tetsushi Sakai. A 20-ps Si Bipolar IC Using Advanced Super Self-Aligned Process Technology with Collector Ion Implantation, IEEE Transaction on Electron Devices, Vol. ED-36, No. 7, pp. 1370-1374, 1989.
• H. Miki, Y. Omura, T. Ohmameda, M. Kumon, K. Asada, T. Sugano, K. Izumi, Tetsushi Sakai. Fabrication and Characterization of a Quarter Micron Gate CMOS Using Ultra-thin Si Film(30nm) on SIMOX Substrates, International Electron Devices Meeting, pp. 906-908, 1989.
• Tetsushi Sakai, K. Murase, S. Konaka. Prospect of SiHBT for High Speed LSI's, Extended Abstracts of the 21th Conference on Solid State Devices (invite), pp. 353-356, 1989.
• 小中信典, 山本栄一, 佐久間一人, 雨宮好仁, 酒井徹志. 超高速シリコンバイポーラIC技術：SST-1B, 電子情報通信学会論文誌, Vol. C-2, No. J-72-C-2(5), pp. 504-509, 1989.
• H. Ichino, S. Konaka, M. Suzuki, T. Wakimoto, Tetsushi Sakai. Super Self-Aligned Process Technology(SST) and Its Applications, Proceedings of the 1988 Bipolar/BiCMOS Circuits and Technology Meeting, pp. 15-18, 1988.
• Y. Kobayashi, C. Yamaguchi, Y. Amemiya, Tetsushi Sakai. High Performance LSI Process Technology:SST CBi-CMOS, International Electron Devices Meeting, pp. 760-763, 1988.
• C. Yamaguchi, Y. Kobayashi, Tetsushi Sakai. A 7GHz PNP Transistor for Complementary Bipolar LSI, Symposium on VLSI Tech. Dig. Tech. Papers , pp. 18-21, 1987.
• S. Konaka, Y. Amemiya, K. Sakuma, Tetsushi Sakai. A 20ps/G Si Bipolar IC Using SST with Collector Ion Implantation, Extended Abstracts of the 19th Conference on Solid State Devices , pp. 331-334, 1987.
• Y. Tanabe, Y. Kobayashi, Y. Yamamoto, Tetsushi Sakai. Device Structure and Electrical Chracteristics of SST-CMOS, Extended Abstracts of the 19th Conference on Solid State Devices , pp. 343-347, 1987.
• H. Miyanaga, S. Konaka, Y. Kobayashi, Y. Yamamoto, Tetsushi Sakai. A 0.85-ns 1-Kbit ECL RAM , IEEE Journal of Solid-State Circuits, Vol. SC-21, No. 4, pp. 501-504, 1986.
• S. Konaka, Y. Yamamoto, Tetsushi Sakai. A 30-ps Si Bipolar IC Using Super Self-Aligned Process Technology, IEEE Transaction on Electron Devices, Vol. ED-33, No. 4, pp. 526-531, 1986.
• Y. Yamamoto, H. Miyanaga, T. Amazawa, Tetsushi Sakai. A MoSi2 Schottky Diode for Bipolar LSI's, IEEE Transaction on Electron Devices, Vol. ED-32, No. 7, pp. 1231-1239, 1985.
• Tetsushi Sakai, S. Konaka, Y. Yamamoto, M. Suzuki. Prospects of SST Technology for High Speed LSI, International Electron Devices Meeting Technology Digest (invite), pp. 18-21, 1985.
• Tetsushi Sakai. Recent Advances in High Speed Bipolar LSI Technology (invite), Extended Abstracts of the 17th Conference on Solid State Devices, pp. 373-376, 1985.
• Y. Kobayashi, Y. Yamamoto, Tetsushi Sakai. A New Bipolar Transistor Structure for Very High Speed VLSI, Symposium on VLSI Tech. Dig. Tech. Papers , pp. 40-41, 1985.
• M. Suzuki, S. Konaka, H. Ichino, Tetsushi Sakai, S. Horiguchi. Design and Application of a 2500-Gate Bipolar Macrocell Array, IEEE Journal of Solid-State Circuits, Vol. SC-20, No. 5, pp. 1025-1031, 1985.
• Y. Tamamoto, H. Miyanaga, Tetsushi Sakai. Schottky Diodefor Bipolar LSI's Consisting of an Impurity-Controiied Si Substrate and AL(2%Si)Electrode, IEEE Transaction on Electron Devices, Vol. ED-32, No. 4, pp. 766-772, 1985.
• S. Konaka, M. Suzuki, Y. Yamamoto, Tetsushi Sakai. Super Self-Aligned Process Technology(SST) for Si Bipolar Devices, Solide State Devices , pp. 23-32, 1985.
• S. Horiguchi, M. Suzuki, H. Ichino, S. Konaka, Tetsushi Sakai. An 80ps 2500-Gate Bipolar Macrocell Array, International Solid State Circuits Conference Digest of Technical Papers, pp. 198-199, 1985.
• S. Konaka, Y. Yamamoto, Tetsushi Sakai. A 30ps Si Bipolar IC Using Super Sel-Aligned Process Technology, Extended Abstracts of the16th Conference on Solid State Devices, pp. 209-212, 1984.
• H. Miyanaga, Y. Kobayashi, S. Konaka, Y. Yamamoto, Tetsushi Sakai. A 1.1ns Access Time 4Kb Bipolar RAM Using Super Self-Aligned Technology, Symposium VLSI Tech. Dig. Tech. Papers, pp. 50-51, 1984.
• H. Miyanaga, S. Konaka, Y. Yamamoto, Tetsushi Sakai. A 0.85ns 1Kb Bipolar ECL RAM, Extended Abstracts of the16th Conference on Solid State Devices, pp. 225-228, 1984.
• H. Miyanaga, Y. Yamamoto, Y. Kobayashi, Tetsushi Sakai. A 1.5ns 1K Bipolar RAM Using Novel Circuit Design and SST-2 Technology, IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 3, pp. 291-298, 1984.
• Y. Yamamoto, H. Miyanaga, Tetsushi Sakai. A 1.5ns 1Kbit Bipolar RAM , Tech. Digest of ESSCIRC, pp. 93-96, 1983.
• Tetsushi Sakai, S. Konaka, Y. Kobayashi, M. Suzuki, Y. Kawai. Gigabit Logic Bipolar Technology: Advanced Super Self-Alighned Process Technology, Electronics Letters, Vol. 19, No. 8, pp. 283-284, 1983.
• Tetsushi Sakai, M. Suzuki. Super Self-Aligned Bipolar Technology (invite), Symposium VLSI Tech. Dig. Tech. Papers, pp. 16-19, 1983.
• M. Ohara, T. Kamoto, Tetsushi Sakai. Very Wide-Band Silicon Bipolar Monolithic Amplifiers, Japanese Journal of Applied Physics, Vol. 22, No. Supplement 22-1, pp. 129-132, 1983.
• H. Yamauchi, T. Nikaidou, T. Nakashima, Y. Kobayashi, Tetsushi Sakai. 10ns 8×8 Multiplier LSI Using Super Self-Aligned Process Technology　, IEEE Journal of Solid-State Circuits, Vol. SC-18, No. 2, pp. 204-210, 1983.
• 山内寛紀, 二階堂忠信, 中島孝利, 小林由治, 酒井徹志. 完全拡張機能を内蔵した超高速8×8ビット乗算器LSI, 電子情報通信学会論文誌, Vol. J66-C, No. 5, pp. 353-360, 1983.
• M. Ohara, T. Kamoto, Tetsushi Sakai. Very Wide-Band Silicon Bipolar Monolithic Amplifiers, Extended Abstracts of the 14th Coference on Solid State Devices, pp. 129-130, 1982.
• S. Konaka, M. Tabe, Tetsushi Sakai. A New Silicon-on-Insulator Structure Using Molecular Beam Epitaxial Growth on Porous Silicon, Appl. Phys. Lett., Vol. 41, No. 1, pp. 86, 1982.
• Tetsushi Sakai, Y. Yamamoto, Y. Kobayashi, K. Kawarada, Y. Inabe, T. Hayashi, H. Miyanaga. A 3ns 1Kbit RAM Using Super Self-Aligned Process Technology, International Solid State Circuits Conference Digest of Tech. Papers, pp. 216-217, 1981.
• Tetsushi Sakai, Y. Yamamoto, Y. Kobayashi, K. Kawarada, Y. Inabe, T. Hayashi, H. Miyanaga. A 3-ns 1-Kbit RAM Using Super Self-Aligned Process Technology, IEEE Trans. on Solid-State Circuits, Vol. SC-16, No. 5, pp. 424-429, 1981.
• Tetsushi Sakai, Y. Kobayashi, H. Yamauchi, M. Sato, T. Makino. High Speed Bipolar ICs Using Super Self-Aligned Process Technology, Japanese Journal of Applide Physics, Vol. 20, No. Sup. 20-1, pp. 155-159, 1981.
• H. Nakamura, Tetsushi Sakai. Bipolar Technologies for High Speed VLSIs, Symposium VLSI Tech. Dig. Tech. Papers, pp. 36-37, 1981.
• Tetsushi Sakai, Y. Kobayashi, H. Yamauchi, M. Sato, T. Makino. High Speed Bipolar ICs Using Super Self-Aligned Process Technology, Extended Abstracts of the 14th Coference on Solid State Devices, pp. 67-68, 1980.
• Tetsushi Sakai, Y. Yamamoto, Y. Kobayashi, H. Yamauchi, T. Ishitani, T. Sudo. Elevated Electrode Integrated Circuits, IEEE Journal of Solid-State Circuits, Vol. SC-14, No. 2, pp. 301-307, 1979.
• Tetsushi Sakai, Y. Sunohara, Y. Sakakibara, J. Murota. Stepped Electrode Transistor: SET, Japanese Journal of Applide Physics, Vol. 16, No. Sup. 16-1, pp. 43-46, 1977.
• Tetsushi Sakai, Y. Yamamoto, Y. Kobayashi, H. Yamauchi, T. Ishitani, T. Sudo. A 100ps Bipolar Logic, International Solid State Circuits Conference Digest of Tech. Papers, pp. 196-197, 1977.
• N. Tsuzuki, Y. Saito, Tetsushi Sakai. A 4GHz 12W Transistor Amplifier Utilizing a New Self-Aligned Bipolar Structure, International Solid State Circuits Conference Digest of Tech. Papers, pp. 162-163, 1977.
• Y. Kobayashi, Tetsushi Sakai, Y. Arita. Subnanosecond ED MOS IC using New Technology , International Electron Devices Meeting Tech. Digest, pp. 597-599, 1977.
• Tetsushi Sakai, Y. Sunohara, Y. Sakakibara, J. Murota. Stepped Electrode Transistor, Extended Abstracts of the 8th Coference on Solid State Devices, pp. 13-14, 1976.

著書

• 応用物理学会, 酒井徹志担当部；第10章10.1概説, 半導体プロセス技術の発展, 素子形成技術. 第2版応用物理ハンドブック, 丸善, 丸善, pp. 第10章10.1, 2002.
• 豊田博夫, 泉勝利, 酒井徹志, 井野正行, 井上靖朗, 小池恵一, 崎山恵三, 武谷健, 日月鷹治, 土屋敏章, 道関隆国, 吉見信. SIMOX LSI 技術, ハイテクノロジー推進研究所, ハイテクノロジー推進研究所, 1998.
• 酒井徹志, 小切間正彦, 山本庸介, 荻野俊郎, 田部道晴, 前田正彦, 河合義夫, 佐藤政明, 酒井芳男, 西前仁也, 清水博文, 青島孝明, 伊藤勝彦, 鈴木道夫. 超LSIの製造技術（教育用ビデオテープ全５巻とテキスト）, 日刊工業新聞社, 日刊工業新聞社, 1990.
• 菅野卓雄, 永田穣, 向井久和, 酒井徹志, 安斉昭夫, 樋口久幸, 宇佐美光雄, 早坂昭夫, 鳥谷部達, 玉置洋一, 川村雅雄, 玉木亮, 本間紀之, 大塚賢治, 榎本実. 超高速バイポーラ・デバイス, 培風館, 培風館, 1985.

国内会議発表 (査読なし・不明)

• 川下道宏, 山崎浩史, 大見俊一郎, 櫻庭政夫, 室田淳一, 酒井徹志.. TML-MOSFETにおける極微細3次元チャネル形成プロセスの検討, 第53回応用物理学関係連合講演会講演予稿集, Vol. 2, pp. 934, Mar. 2006.
• 川下道宏, 大見俊一郎, 櫻庭政夫, 室田淳一, 酒井徹志.. TML(Twin-Multi-Layer Channel) MOSFETの作製プロセスに関する検討, 第66回応用物理学会学術講演会講演予稿集, Vol. 2, pp. 741, Sept. 2005.
• 川下道宏, 山崎浩史, 袴田佳孝, 大見俊一郎, 櫻庭政夫, 室田淳一, 酒井徹志.. 新構造TML(Twin-Multi-Layer Channel)MOSFET, 第52回応用物理学関係連合講演会講演予稿集, Vol. 2, pp. 982, Mar. 2005.

特許など

• 酒井徹志, 加藤　樹里, 岡　秀明, 金本　啓, 原　寿樹. 半導体装置の製造方法. 特許. 登録. 国立大学法人東京工業大学, セイコーエプソン株式会社. 2006/03/15. 特願2006-071328. 2007/03/01. 特開2007-053332. 特許第4231909号. 2008/12/19 2008.
• 酒井徹志, 加藤　樹里, 岡　秀明, 金本　啓, 原　寿樹. 半導体装置および半導体装置の製造方法. 特許. 登録. 国立大学法人東京工業大学, セイコーエプソン株式会社. 2005/09/30. 特願2005-288877. 2007/04/19. 特開2007-103490. 特許第4644577号. 2010/12/10 2010.
• 酒井徹志, 加藤　樹里, 岡　秀明, 金本　啓, 原　寿樹. 半導体装置および半導体装置の製造方法. 特許. 公開. 国立大学法人東京工業大学, セイコーエプソン株式会社. 2005/09/30. 特願2005-288878. 2007/04/19. 特開2007-103491. 2007.
• 酒井徹志, 加藤　樹里, 原　寿樹, 金本　啓. 半導体装置および半導体装置の製造方法. 特許. 公開. 国立大学法人東京工業大学, セイコーエプソン株式会社. 2005/09/30. 特願2005-288876. 2007/04/19. 特開2007-103489. 2007.
• 酒井徹志, 原　寿樹, 加藤　樹里, 岡　秀明, 金本　啓. 半導体装置の製造方法. 特許. 公開. 国立大学法人東京工業大学, セイコーエプソン株式会社. 2005/08/26. 特願2005-246124. 2007/03/08. 特開2007-059804. 2007.
• 酒井徹志, 原　寿樹. 半導体基板の製造方法及び、半導体装置の製造方法. 特許. 登録. 国立大学法人東京工業大学, セイコーエプソン株式会社. 2005/08/10. 特願2005-231849. 2007/02/22. 特開2007-048949. 特許第4852275号. 2011/10/28 2011.
• 酒井徹志, 岡　秀明, 加藤　樹里, 原　寿樹, 金本　啓. 半導体装置の製造方法. 特許. 登録. 国立大学法人東京工業大学, セイコーエプソン株式会社. 2005/07/22. 特願2005-212747. 2007/02/08. 特開2007-035701. 特許第4726120号. 2011/04/22 2011.
• 酒井徹志, 金本　啓, 原　寿樹, 岡　秀明, 加藤　樹里. 半導体基板の製造方法及び、半導体装置の製造方法. 特許. 登録. 国立大学法人東京工業大学, セイコーエプソン株式会社. 2005/07/20. 特願2005-209809. 2007/02/01. 特開2007-027542. 特許第4649282号. 2010/12/17 2010.
• 酒井徹志, 大見俊一郎, 山崎　崇. 半導体基板、半導体装置及び半導体基板の作成方法. 特許. 公開. 国立大学法人東京工業大学. 2004/10/04. 特願2005-514563. 2005/04/21. 特再表2005-036638. 2005.

学位論文

• 超高速Siバイポーラトランジスタの構造・製造方法と超高速LSIへの応用に関する研 究,  本文,  Doctor of Engineering,  北海道大学,  1998/--/--, 

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