Journal Paper

• Y. Ito, S. Tamai, T. Hoshi, T. Gotow, Y. Miyamoto. Dependence of Process Damage on GaN Channel Thickness in AlGaN/GaN High-electron-mobility Transistors with Back-barrier Layers, JPN. J. APPL. PHYS., vol. 62, no. SC, SC1048, Feb. 2023.
• J. Kotani, K. Makiyama, T. Ohki, S. Ozaki, N. Okamoto, Y. Minoura, M. Sato, N. Nakamura, Y. Miyamoto. High-Power-Density InAlGaN/GaN HEMT using InGaN back barrier for W-band amplifiers, ELECTRON. LETT., vol. 59, no. 4, e12715, Feb. 2023.
• YASUYUKI MIYAMOTO, Takahiro Gotow. GaN HEMTでの二次元電子ガスキャリヤ濃度と ゲートドレイン間リーク電流理論計算, 電気学会論文誌C, 電気学会, Vol. 142, No. 3, pp. 348-353, Mar. 2022.
• T. Aota, A. Hayasaka, I. Makabe, S. Yoshida, T. Gotow, Y. Miyamoto. Wet etching for isolation of N-polar GaN HEMT structure by electrodeless photo-assisted electrochemical reaction, Japanese Journal of Applied Physics, 60, SCCF06, Mar. 2021.
• Moataz Eissa, Takuya Mitarai, Tomohiro Amemiya, Yasuyuki Miyamoto, Nobuhiko Nishiyama. Fabrication of Si photonic waveguides by electron beam lithography using improved proximity effect correction, Japanese Journal of Applied Physics, IOP publishing, Volume 59, Number 12, p. 126502, Nov. 2020.  Official location  
• Yasuyuki Miyamoto, Takahiro Gotow. Simulation of short channel effect in GaN HEMT with a combined thin undoped channel and semi-insulating layer, IEICE Transactions on Electronics, Vol. 103.C, Page 304-307, June 2020.
• K. Fukuda, N. Nogami, S. Kunisada, Y. Miyamoto. Circuit speedoriented device design scheme for GaAsSb / InGaAs double gatehetero-junction tunnel FETs, Jpn. J. Appl. Phys., 59, SGGA06 (2020), Feb. 2020.  Official location  
• Y. Miyamoto, T. Kanazawa, N. Kise, H. Kinoshita, K. Ohsawa. Regrown Source/Drain in InGaAs Multi-Gate MOSFETs, J. Crystal Growth, vol. 522, （2019）11-15, Sept. 2019.  Official location  
• K. Hotta, Y. Tomizuka, K. Itagaki, I. Makabe, S. Yoshida, Y. Miyamoto. Annealing temperature dependence of alloy contact for N-polar GaN HEMT structure, Jpn. J. Appl. Phys, 58, (2019), SC, SCCD14, May 2019.
• W Zhang, T. Kanazawa, Y. Miyamoto. Performance improvement of a p-MoS2/HfS2 van der Waals heterostructure tunnelling field-effect transistor by UV-O3 treatment, Apl. Phys. Exp, vol. 12, no. 6, 065005 (2019), May 2019.  Official location  
• R. Aonuma, N. Kise, Y. Miyamoto. GaAsSb/InGaAs double-gate vertical tunnel FET with a subthreshold slope of 56 mV/dec at room temperature, Jpn. J. Appl. Phys., 58, SBBA08 (2019), Mar. 2019.
• W Zhang, S. Netsu, T. Kanazawa, T. Amemiya, Y. Miyamoto. Effect of increasing gate capacitance on the performance of a p-MoS2/HfS2 van der Waals heterostructure tunneling field-effect transistor, Jpn. J. Appl. Phys, 58, SBBH02 (2019), Jan. 2019.
• Seiko Netsu, Toru Kanazawa, Teerayut Uwanno, Tomohiro Amemiya, Kosuke Nagashio, Yasuyuki Miyamoto. Type-II HfS2/MoS2 Heterojunction Transistors, IEICE Transactions on Electronics, Vol. E101-C, No. 5, pp. 338-342, May 2018.  Official location  
• S. Netsu, M. Hellenbrand, C. B. Zota, Y. Miyamoto, E. Lind. A Method for Determining Trap Distributions of Specific Channel Surfaces in InGaAs Tri-gate MOSFETs, IEEE Journal of the Electron Devices Society, Vol. 6, issue. 1, pp. 408-412 (2018)., Feb. 2018.
• Toru Kanazawa, Tomohiro Amemiya, Vikrant Upadhyaya, Atsushi Ishikawa, Kenji Tsuruta, Takuo Tanaka, Yasuyuki Miyamoto. Performance Improvement of HfS2 Transistors by Atomic Layer Deposition of HfO2, IEEE Transactions on Nanotechnology, Vol. 16, No. 4, pp. 582-587, July 2017.
• Vikrant UPADHYAYA, Toru KANAZAWA, Yasuyuki MIYAMOTO. Vacuum Annealing and Passivation of HfS2 FET for Mitigation of Atmospheric Degradation, IEICE Transactions on Electronics, Vol. E100-C, No. 5, pp. 453-457, May 2017.  Official location  
• K. Ohsawa, S. Netsu, N. Kise, S. Noguchi, Y. Miyamoto. Dependence of electron mobility on gate voltage sweeping width and deposition temperature in MOSFETs with HfO2/Al2O3/InGaAs gate stacks, Jpn. J. Appl. Phys., vol. 56, no. 4S, 04CG05 2017, Mar. 2017.
• A. Yukimachi, Y. Miyamoto. InGaAs/AlAs triple-barrier p-i-n junction diode for realizing superlattice-based FET for steep slope, Jpn. J. Appl. Phys., vol. 55, 118004, Oct. 2016.
• Y. Miyamoto. Recent progress in compound semiconductor electron devices (Review paper), IEICE Electronics Express, Vol. 13(2016), No. 18, pp. 1-13, Sept. 2016.  Official location  
• Nobukazu Kise, Haruki Kinoshita, Atsushi Yukimachi, Toru Kanazawa, Yasuyuki Miyamoto. Fin width dependence on gate controllability of InGaAs channel FinFETs with regrown source/drain, Solid-State Electronics, Vol. 126, pp. 92-95, Sept. 2016.  Official location  
• Toru Kanazawa, Tomohiro Amemiya, YASUYUKI MIYAMOTO. 二次元材料HfS2を用いたMOSトランジスタ, 月刊機能材料, Vol. 36, No. 9, pp. 46-52, Sept. 2016.
• Wenbo Lin, Shinjiro Iwata, Koichi Fukuda, Yasuyuki Miyamoto. Scaling limit for InGaAs/GaAsSb heterojunction double-gate tunnel FETs from the viewpoint of direct band-to-band tunneling from source to drain induced off-characteristics deterioration, Japanese Journal of Applied Physics, Vol. 55, No. 7, pp. 070303, June 2016.  Official location  
• Shinjiro Iwata, Kazumi Ohashi, Wenbo Lin, Koichi Fukuda, YASUYUKI MIYAMOTO. GaAsSb/InGaAsダブルゲートンネルFET におけるソースおよびドレイン不純物濃度依存性, 電気学会論文誌C, Vol. 136, no. 4, pp. 467-473, Apr. 2016.
• YASUYUKI MIYAMOTO. III-V族チャネルを持つMOSFET (特集解説), 電気学会論文誌C, vol. 136, no. 4, pp. 437-443, Apr. 2016.
• Toru Kanazawa, Tomohiro Amemiya, Atsushi Ishikawa, Vikrant Upadhyaya, Kenji Tsuruta, Takuo Tanaka, Yasuyuki Miyamoto. Few Layer HfS2 FET, Scientific Reports, Vol. 6, pp. 22277, Mar. 2016.  Official location  
• F. A. Fatah, Y.-C. Lin, R.-X. Liu, K.-C. Yang, T.-W. Lin, H.-T. Hsu, J.-H. Yang, Y. Miyamoto, H. Iwai, C. Hu, S. Salahuddin, E. Y. Chang. A 60-nm-thick enhancement mode In0.65Ga0.35As/InAs/ In0.65Ga0.35As high-electron-mobility transistor fabricated using Au/Pt/Ti non-annealed ohmic technology for low-power logic applications,, Applied Physics Express, Volume 9, 026502, Jan. 2016.
• F. A. Fatah, Y.-C. Lin, T.-Y. Lee, K.-C. Yang, R.-X. Liu, J.-R. Chan, H.-T. Hsu, Y. Miyamoto, E. Y. Chang. Potential of Enhancement Mode In0.65Ga0.35As/InAs/In0.65Ga0.35As HEMTs for Using in High-Speed and Low-Power Logic Applications, Solid State Sci. Technol, volume 4, issue 12, N157-N159, Oct. 2015.
• R Yamanaka, T. Kanazawa, E. Yagyu, Y. Miyamoto. Normally-off AlGaN/GaN high-electron-mobility transistor using digital etching technique, Jpn. J. Appl.Phys., Volume 54, Number S61, June 2015.
• K. Ohashi, M. Fujimatsu, S. Iwata, Y. Miyamoto. Body width dependence of subthreshold slope and on-current in GaAsSb/InGaAs double-gate vertical tunnel FETs, Jpn. J. Appl.Phys., Vol. 54, Number 4S, Apr. 2015.
• Tomohiro Amemiya, Atsushi Ishikawa, Toru Kanazawa, JoonHyun Kang, Nobuhiko Nishiyama, Yasuyuki Miyamoto, Takuo Tanaka, Shigehisa Arai. Permeability-controlled Optical Modulator with Tri-gate Metamaterial: Control of Permeability on InP-based Photonic Integration Platform, Scientific Reports, Vol. 5, pp. 8985, Mar. 2015.
• K. Ohsawa, A. Kato, T. Kanazawa, E. Uehara, Y. Miyamoto. Channel thickness dependence on InGaAs MOSFET with InP source for high current density, IEICE Electronics Express, vol. 11, No. 14, pp. 1-5, July 2014.
• Y. Atsumi, N. Taksatorn, N. Nishiyama, Y. Miyamoto, S. Arai. Loss reduction of Si optical waveguides by beam step-size fracturing technique in electron beam lithography, Japanese Journal of Applied Physics, JSAP, Vol. 53, No. 6, p. 06JB04, May 2014.
• M. Yamada, K. Uchida, Y. Miyamoto. Delay time component of InGaAs MOSFET caused by dynamic source resistance, IEICE Trans. Electron, Vol. E97-C, No. 5, pp. 419-422, May 2014.
• M. Kashiwano, J. Hirai, S. Ikeda, M. Fujimatsu, Y. Miyamoto. High Open-Circuit Voltage Gain in Vertical InGaAs Channel Metal–Insulator–Semiconductor Field-Effect Transistor Using Heavily Doped Drain Region and Narrow Channel Mesa, JPN. J. APPL. PHYS., vol. 54, no. 4, issue 2, 2013.
• K. Hayashi, Y. Yamaguchi, T. Oishi, H. Ostuka, K. Yamanaka, M. Nakayama, Y. Miyamoto. Mechanism Study of Gate Leakage Current for AlGaN/GaN HEMT Structure Under High Reverse Bias by TSB Model and TCAD Simulation, JPN. J. APPL. PHYS., vol. 54, no. 4, issue 2, 2013.
• Takafumi Uesawa, YASUYUKI MIYAMOTO. 縦型 ゲート制御ホットエレクトロントランジスタの新しい遮断周波数算出方法, 電子情報通信学会論文誌, Vol. J96-C, No. 7, pp. 174-179, 2013.
• 林 一夫, 大石 敏之, 加茂 宣卓, Yuutarou Yamaguchi, 大塚 浩志, 山中 宏治, 中山 正敏, YASUYUKI MIYAMOTO. AlGaN/GaN HEMTにおけるドレーン漏れ電流の解析, 電子情報通信学会論文誌. C, エレクトロニクス, Vol. J96-C, No. 8, pp. 200-208, 2013.
• C.-H. Yu, H.-T. Hsu, C.-Y. Chiang, C.-I Kuo, Y. Miyamoto, E. Y. Chang. Performance Evaluation of InGaSb/AlSb P-Channel High-Hole-Mobility Transistor Faricated Using BCl3 Dry Etching, JPN. J. APPL. PHYS., vol. 52, no. 2, 2013.
• E. Y. Chang, C.-I Kuo, H.-T. Hsu, C.-Y. Chiang, Y. Miyamoto. InAs Thin-Channel High-Electron-Mobility Transistors with Very High Current-Gain Cutoff Frequency for Emerging Submillimeter-Wave Applications, Appl. Phys. Exp., vol. 6, no. 3, 2013.
• Atsushi Kato, Toru Kanazawa, Shunsuke Ikeda, Yosiharu Yonai, Yasuyuki Miyamoto. Reduction of access resistance of InP/InGaAs composite-channel MOSFET with back source electrode, IEICE Trans. Electron., vol. E95-C, no. 5, pp. 904-919, May 2012.
• Naoaki Takebe, Y. Miyamoto. Reduction of base-collector capacitance in InP/InGaAs DHBT with buried SiO2 wires, IEICE Trans. Electron., vol. E95-C, no. 5, pp. 917-920, May 2012.
• Hisashi Saito, Y. Miyamoto. Reduction of Output Conductance in Vertical InGaAs Channel Metal?Insulator?Semiconductor Field-Effect Transistor Using Heavily Doped Drain Region, Applied Phys. Exp., vol. 5, no. 2, pp. 24101, Mar. 2012.
• F. Fatah, C.-I Kuo, H.-T. Hsu, C.-Y. Chiang, C.-Y. Hsu, Y. Miyamoto, E. Y. Chang. Bias-Dependent Radio Frequency Performance for 40 nm InAs High-Electron-Mobility Transistor with a Cutoff Frequency Higher than 600 GHz, JPN. J. APPL. PHYS., vol. 51, no. 11, 2012.
• N. Takebe, T. Kobayashi, H. Suzuki, Y. Miyamoto, K. Furuya. Fabrication of InP/InGaAs DHBTs with buried SiO2 wires, IEICE Trans. Electron., IEICE, vol. E94-C, no. 5, pp. 830-834, May 2011.
• M. Yamada, T. Uesawa, Y. Miyamoto, K. Furuya. Deviation from Proportional Relationship between Emitter Charging Time and Inverse Current of Heterojunction Bipolar Transistors Operating at High Current Density, IEEE Electron Device Lett., IEEE, vol. 32, # 4, pp. 491-493, Apr. 2011.
• R. Terao, T. Kanazawa, S. Ikeda, Y. Yonai, A. Kato, Y. Miyamoto. InP/InGaAs Composite MOSFETs with Regrown Source and Al2O3 gate dielectric Exhibiting Maximum Drain Current Exceeding 1.3 mA/μm, Applied Phys. Exp., The Japan Society of Applied Physics, vol. 4, no. 5, 054201, Apr. 2011.
• H. Saito, Y. Matsumoto, Y. Miyamoto, K. Furuya. Vertical InGaAs Channel Metal–Insulator–Semiconductor Field Effect Transistor with High Current Density, Jpn. J. Appl. Phys., vol. 50, no. 1, 014102, Jan. 2011.
• Wang, C.-T., Kuo, C.-I., Hsu, H.-T., Chang, E.Y., Hsu, L.-H., Lim, W.-C., YASUYUKI MIYAMOTO. Flip-chip packaging of low-noise metamorphic high electron mobility transistors on low-cost organic substrate, Japanese Journal of Applied Physics, Vol. 50, No. 9 PART 1, 2011.
• Toru Kanazawa, kazuya wakabayashi, Hisashi Saito, Ryousuke Terao, Shunsuke Ikeda, YASUYUKI MIYAMOTO, KAZUHITO FURUYA. Submicron InP/InGaAs Composite-Channel Metal–Oxide–Semiconductor Field-Effect Transistor with Selectively Regrown n+-Source, Applied Physics Express, Vol. 3, No. 9, 094201, Sept. 2010.
• H. Saito, Y. Miyamoto, K. Furuya. Fabrication of Vertical InGaAs Channel Metal-Insulator-Semiconductor Field Effect Transistor with a 15-nm-wide Mesa Structure and a Drain Current Density of 7 MA/cm2, Applied Phys. Exp., vol. 3, no. 8, p. 084101, Aug. 2010.
• C-I. Kuo, H-T. Hsu, Y-L. Chen, C-Y. Wu, E. Y. Chang, Y. Miyamoto, W-C. Tsern, K. C. Sahoo. RF Performance Improvement of Metamorphic High-Electron Mobility Transistor Using (InxGa1 - xAs)m/(InAs)n Superlattice-Channel Structure for Millimeter-Wave Applications, IEEE Electron Device Letters, vol. 31, no. 7, pp. 677-679, July 2010.
• Y. Miyamoto, S. Takahashi, T. Kobayashi, Hiroyuki Suzuki, K. Furuya. Estimation of collector current spreading in InGaAs SHBT having 75-nm-thick collector, IEICE Trans. Electron., 電子情報通信学会, vol. E93C, no. 5, pp. 644-647, May 2010.
• Chia-Ta Chang, Heng-Tung Hsu, Edward Yi Chang, Chien-I Kuo, Jui-Chien Huang, Chung-Yu Lu, Yasuyuki Miyamoto. 30-GHz Low-Noise Performance of 100-nm-Gate-Recessed n-GaN/AlGaN/GaN HEMTs, IEEE Electron Device Letters, Vol. 31, No. 2, pp. 105 - 107, Feb. 2010.
• Takafumi Uesawa, Masayuki Yamada, Yasuyuki Miyamoto, Kazuhito Furuya. Monte Carlo Analysis of Base Transit Times of InP/GaInAs Heterojunction Bipolar Transistors with Ultrathin Graded Bases, Japanese Journal of Applied Physics, 応用物理学会, Vol. 49, 024302, Feb. 2010.
• Kuo, C.-I., Hsu, H.-T., Chang, E.Y., YASUYUKI MIYAMOTO, Wu, C.-Y., Chen, Y.-L., Hsiao, Y.-L.. DC and RF performance improvement of 70nm quantum well field effect transistor by narrowing source - drain spacing technology, Japanese Journal of Applied Physics, Vol. 49, No. 1 Part 1, 2010.
• Chia-Yuan Chang, Heng-Tung Hsu, Edward Yi Chang, Hai-Dang Trinh, Yasuyuki Miyamoto. InAs-Channel Metal-Oxide-Semiconductor HEMTs with Atomic-Layer-Deposited Al2O3 Gate Dielectric, Electrochemical and Solid-State Letters,, vol. 12, no. 12, pp. H456-H459, Dec. 2009.
• Chia-Yuan Chang, Heng-Tung Hsu, Edward Yi Chang, YASUYUKI MIYAMOTO. InAs-Channel High-Electron-Mobility Transistors for Ultralow-Power Low Noise Amplifier Applications, Japanese Journal of Applied Physics, Volume 48, No. 4, Issue 2, 04C094 (3 pages), Apr. 2009.
• Hisashi Saito, Yasuyuki Miyamoto, Kazuhito Furuya. Improvement in Gate Insulation in InP Hot Electron Transistors for High Transconductance and High Voltage Gain, Applied Physics Express, The Japan Society of Applied Physics, Vol. 2, No. 3, 034501, Mar. 2009.
• So Nishimura, KAZUHITO FURUYA, YASUYUKI MIYAMOTO. Design and Simulation of Hot-Electron Diffraction Oservation by Scanning Probe – Quantitative Evaluation of Observation Possibility –, Jpn. J. Appl.Phys., vol. 47, no. 9, pp. 8652-8658, Nov. 2008.
• So Nishimura, KAZUHITO FURUYA, YASUYUKI MIYAMOTO. Design and Simulation of Hot-Electron Diffraction Oservation by Scanning Probe – Quantitative Evaluation of Observation Possibility –, Jap. J. Appl. Phys., vol. 47, no. 9, pp. 8652-8658, Nov. 2008.
• Chien-I KUO, Heng-Tung HSU, Edward Yi CHANG, Yasuyuki MIYAMOTO, Wen-Chung TSERN. InAs High Electron Mobility Transistors with Buried Gate for Ultralow-Power-Consumption Low-Noise Amplifier Application, Japanese Journal of Applied Physics, The Japan Society of Applied Physics, Vol. 47, No. 9, pp. 7119–7121, Sept. 2008.
• Chien-I Kuo, Heng-Tung Hsu, Edward Yi Chang, Chia-Yuan Chang, Yasuyuki Miyamoto, Suman Datta, Marko Radosavljevic, Guo-Wei Huang, Ching Ting Lee. RF and Logic Performance Improvement of In0.7Ga0.3As/InAs/In0.7Ga0.3As composite channel HEMTs Using Gate-Sinking Technology, IEEE Electron Device Lett., IEEE, vol. 29, no. 4, pp. 290-293, Apr. 2008.
• Mitsuhiko Igarashi, KAZUHITO FURUYA, YASUYUKI MIYAMOTO. Cutoff Frequency Characteristics of Gate-Control Hot Electron Transistors by Monte Carlo Simulation, Physica Status Solidi(C), vol. 5, no. 1, p. 70, Jan. 2008.
• Chia-Yuan Chang, Heng-Tung Hsu, Edward Yi Chang, Chien-I Kuo, Suman Datta, Marko Radosavljevic, YASUYUKI MIYAMOTO, Guo-Wei Huang. Investigation of Impact Ionization in InAs-Channel HEMT for High-Speed and Low-Power Applications, IEEE Electron Dev. Lett., vol. 28, no. 10, pp. 856-858, Oct. 2007.
• Kazuya Nishihori, Yasuyuki Miyamoto. Numerical Analysis of the Effect of P-Regions on the I-V Kink in GaAs MESFETs, Trans. IECE of Japan, vol. E90-C, no. 8, pp. 1643-1649, Aug. 2007.
• Chia-Yuan Chang, Edward Yi Chang, Yi-Chung Lien, Yasuyuki Miyamoto, Chien-I Kuo, Sze-Hung Chang, Li-Hsin Chu. High-PerformanceIn0.52Al0.48As/In0.6Ga0.4As Power Metamorphic High Electron Mobility Transistor for Ka-Band Applications, Jpn. J. Appl. Phys., Vol. 46, No. 6A, pp. 3385-3387, June 2007.
• Y. Miyamoto, M. Ishida, T. Yamamoto, T. Miura, K. Furuya. InP buried growth of SiO2 wires toward reduction of collector capacitance in HBT, J. Cryst, Growth, Vol. 298, pp. 867–870, 2007.
• A. Suwa, I. Kashima, Y. Miyamoto, K. Furuya. Increase of collector current in hot electron transistors controlled by gate bias, Jpn. J. Appl. Phys.,, Vol. 46, No. 9, pp. L202-L204, 2007.
• Nobuya Machida, Yasuyuki Miyamoto, Kazuhito Furuya. Charging Time of Double-Layer Emitter in Heterojunction Bipolar Transistor Based on Transmission Formalism, Jpn. J. Appl. Phys., Vol. 45, No. 35, pp. L935 - L937, Sept. 2006.
• K Furuya, N Machida, M Igarashi, R Nakagawa, I Kashima, M Ishida, Y Miyamoto. MC simulation of ultrafast transistor using ballistic electron in intrinsic semiconductor and its fabrication feasibility, J. Physics: Conference Series, Vol. 38, pp. 208-211, 2006.
• Kazuhito Furuya, Yasunori Ninomiya, Nobuya Machida, Yasuyuki Miyamoto. Double-Slit Interference Observation of Hot Electrons in Semiconductors -- Analysis of Experimental Data --, Jpn. J. Appl. Phys., Vol. 44, No. 5A, pp. 2936-2944, May 2005.
• K. Goto, T. Kirigaya, Y. Masuda, Y.-J. Kim, Y. Miyamoto, S. Arai. Design and Experiments of a Near-Field Optical Disk Head for Very High Efficiency, The Journal of Scanning Microscopies, Vol. 26, No. 5, pp. I68-I72, May 2004.
• Masaki Yoshizawa, Shigeru Moriya, Hiroyuki Nakano, Yuichi Shirai, Tatsuo Morita, Tetsuya Kitagawa, Yasuyuki Miyamoto. Impact of Latent Image Quality on Line Edge Roughness in Electron Beam Lithography, Jpn. J. Appl. Phys. , Vol. 43, No. 6B, pp. 3739, 2004.
• Y. Miyamoto, Y. Shirai, M. Yoshizawa, K. Furuya. 20 nm Periodical Pattern by Calixarene Resists: Comparison of CMC[4]AOMe with MC[6]AOAc, 2004 International Microprocesses and Nanotechnology Conference, 28P-6-54, 2004.
• Katsuhiko Takeuchi, Hiroshi Maeda, Ryo Nakagawa, Yasuyuki Miyamoto, Kazuhito Furuya. InP hot-electron transistors with emitter mesa fabricated between gate electrodes for reduction in emitter-gate gate-leakage current, Jpn. J. Appl. Phys., Vol. 43, No. 2A, pp. L183, 2004.
• YASUYUKI MIYAMOTO. Observation of current modulation through self-assembled monolayer molecule in transistor structure, Jpn. J. Appl. Phys., Vol. 43, No. 3A, pp. L337, 2004.
• K. Goto, T. Kirigaya, Y. Masuda, Y.-J. Kim, Y. Miyamoto, S. Arai . Design and Experiments of a Near-Field Optical Disk Head for Very High Efficiency, The Journal of Scanning Microscopies, Vol. 26, No. 5, pp. I-68, 2004.
• Masaki Yoshizawa, Yasuyuki Miyamoto, Hiroyuki Nakano, Tetsuya Kitagawa, Shigeru Moriya. Challenges to ultra-thin resist process for LEEPL, J. Photopolymer Sci. Technol., Vol. 17, pp. 581, 2004.
• R.Nakagawa, K.Takeuchi, Y.Yamada, Y.Miyamoto, K.Furuya. InP Hot Electron Transistors with Reduced Emitter Width for Controllability of Collector Current by Gate Bias, International Conference on Indium Phosphide and Related Material, Vol. P1-14, 2004.
• K. Furuya, Y. Ninomiya, Y. Miyamoto. Young's Double-Slit Interference Experiment of Hot Electron　in Semiconductors, The 13th International Conference on Nonequilibrium Carrier Dynamics in Semiconductors, Vol. Th11.17, 2003.
• Yasuyuki Miyamoto, Ren Yamamoto, Hiroshi Maeda, Katsuhiko Takeuchi, Nobuya Machida, Lars-Erik Wernersson, Kazuhito Furuya. InP Hot Electron Transistors with a Buried Metal Gate, Jpn. J. Appl. Phys., Vol. 42, No. 12, pp. 7221, 2003.
• Tsuyoshi Tanaka, Kohichi Tokudome, Yasuyuki Miyamoto. Effects of Low-Oxygen-Content Metalorganic Precursors on AlInAs and High Electron Mobility Transistor Structures with the Thick AlInAs Buffer Layer, Jpn. J. Appl. Phys., Vol. 42, No. 8B, pp. L993, 2003.
• Y. Miyamoto, Y. Tohmori. Activities of Indium Phosphide in Japan, GaAs Mantech, Vol. 11-1, 2003.
• 田中剛, 徳留功一, 宮本恭幸. 低酸素MOVPE材料を用いたAlInAs,InPとAlInAs/InP HEMT構造の成長, 第50回応用物理学会関係連合講演会, Vol. 28p-YA-3, 2003.
• Y. Miyamoto, K. Sasao, Y. Azuma, N. Kaneda, Y. Majima. Small Au/SAM/Au junctions by EB lithography, Photonic West, 4999-37, 2003.
• K.Yokoyama, Y.Miyamoto, T.Morita, T.Arai, K.Matsuda, K.Furuya. Wet etching for self-aligned 0.1-um-wide emitter in InP/InGaAs HBT, Topical Workshop on Heterostructure Microelectronics, Vol. W-11, 2003.
• K. Sasao, Y. Azuma, N. Kaneda, E. Hase, Y. Miyamoto, Y. Majima. Observation of current modulation in SAM-FET fabricated by an air-bridge structure, The 2003 International Conference on Solid State Devices and Materials, Vol. P7-5, 2003.
• K. Takeuchi, H. Maeda, R. Makagawa, Y. Miyamoto, K. Furuya. InP hot electron transistors using modulation of gate electrodes, The 2003 International Conference on Solid State Devices and Materials, Vol. E-7-3, 2003.
• M. Yoshizawa, S. Moriya, H. Nakano, T. Morita, T. Kitagawa, Y. Miyamoto. The Impact of Latent Image Quality on Line Edge Roughness in Electron Beam Lithography, 2003 International Microprocesses and Nanotechnology Conference, Vol. 30p-6-15, 2003.
• Keigo Yokoyama, Koji Matuda, Toshihiro Nonaka, Yasuyuki Miyamoto, Kazuhito Furuya. Fabrication of GaInAs/InP heterojunction bipolar transistors with a single tungsten wire as collector electrode, Jpn. J. Appl. Phys., Vol. 42, No. 12B, pp. L1501, 2003.
• 二宮泰徳, 中村弘道, 宮本恭幸, 町田信也, 古屋一仁. GaInAs/InPダブルスリットを通過したホットエレクトロンの電流変調, 第49回応用物理学会関係連合講演会, Vol. 27p-YH-16, 2002.
• 真島豊, 笹尾和樹, 東康男, 宮本恭幸. 金属/SAM/金属構造素子の試作と電流-電圧特性, 第63回応用物理学会学術講演会, Vol. 25a-ZF-11, 2002.
• 田中剛, 徳留功一, 宮本恭幸. 低酸素MOCVD材料を用いたAlInAsとAlInAs/InP HEMT構造の成長, 第63回応用物理学会学術講演会, Vol. 26p-YD-14, 2002.
• 前田寛, 山本練, 竹内克彦, 宮本恭幸, 古屋一仁. ノンドープInP中の埋込金属周期電極構造を用いたホットエレクトロントランジスタ, 第63回応用物理学会学術講演会, Vol. 25p-P9-7, 2002.
• Y. Miyamoto, H. Nakamura, Y. Ninomiya, H. Oguchi, N. Machida, K. Furuya . Current modulation in fine electrode by hot electron passing through GaInAs/InP double slits, International Conference on Indium Phosphide and Related Materials, Vol. PII-24, 2002.
• Y. Miyamoto, T. Arai, S. Yamagami, K. Matsuda, K. Furuya. Evaluation of base-collector capacitance in submicron buried metal heterojunction bipolar transistors , The 2002 International Conference on Solid State Devices and Materials, Vol. E-1-4, 2002.
• T. Morita, T. Arai, H. Nagatsuka, Y. Miyamoto, K. Furuya. Fabrication of InP/GaInAs Double Heterojunction Bipolar Transistors with 0.1-um-Wide Emitter, Jpn. J. Appl. Phys., Vol. 41, No. 2A, pp. L121, 2002.
• 宮本恭幸, 古屋一仁. InP系ヘテロ接合バイポーラトランジスタの高速化技術, 応用物理, Vol. 71, No. 3, pp. 285, 2002.
• Y. Miyamoto, R. Yamamoto, H. Maeda, K. Takeuchi, L.-E. Wernersson, K, Furuya. InP Hot Electron Transistor with a Buried Metallic Gate for Electron Emission, 60th Annual Device Research Conference, Vol. III-20, 2002.
• K. Takeuchi, R. Yamamoto, H. Maeda, Y. Miyamoto, K. Furuya. Freestanding tungten wires for BM-HET , 2002 International Microprocesses and Nanotechnology Conference, Vol. 6B-3-4, 2002.
• Y. Majima, K. Sasao, Y. Azuma, Y. Miyamoto. Fabrication and I-V characteristics of metal/SAM/metal devices, 2002 International Microprocesses and Nanotechnology Conference, Vol. 6B-3-7, 2002.
• T. Arai, S. Yamagami, Y. Miyamoto, KAZUHITO FURUYA. Reduction of Base-Collector Capacitance in Submicron InP/GaInAs Heterojunction Bipolar Transistors with Buried Tungsten Wires, Jpn. J. Appl. Phys., Vol. 40, No. 7B, pp. L735, July 2001.
• Y.Miyamoto, H.Oguchi, H.Nakamura, Y.Ninomiya, K.Furuya. Isolation of 80 nm periodical Au/Ti/n-GaInAs ohmic contacts, 20th Electronic Materials Symposium, B3, 2001.
• 森田竜夫, 新井俊希, 長塚弘美, 宮本恭幸, 古屋一仁. 0.1μｍ幅エミッタを有するInP/GaInAs系DHBTの作製, 第62回応用物理学会学術講演会, Vol. 13p-ZF-9, 2001.
• 前堅一, 柄沢伸也, 宮本恭幸, 古屋一仁. GaAs/AlAs/InGaPショットキーコンタクト構造真空エミッタ, 第62回応用物理学会学術講演会, Vol. 13a-M-3, 2001.
• Y. Miyamoto, M. Kurita, K. Furuya. GaInAs/AlAs/InP hot electron vacuum emitter, 1st International Workshop on Quantum Nonplaner Nanostructures & Nanoelectronics, Tu-P30, 2001.
• 新井俊希, 山上滋春, 酒井隆史, 宮本恭幸, 古屋一仁. BM-HBT高速化のためのコレクタ抵抗の低減, 第48回応用物理学会関係連合講演会, Vol. 28p-YC-8, 2001.
• Y. Miyamoto, H. Oguchi, H. Nakamura, Y. Ninomiya, K. Furuya. 80 nm periodical ohmic contacts toward Young's double slit experiment using a semiconductor, 1st International Workshop on Quantum Nonplaner Nanostructures & Nanoelectronics, Tu-P31, 2001.
• 山本練, 宮本恭幸, 古屋一仁, E. リンド, I.ピッツンカ, Ｌ.バナソン, L.サミュエルソン. ノンドープGaAs中の埋込み金属電極によるホットエレクトロン電流変調, 第48回応用物理学会関係連合講演会, Vol. 29a-YD-3, 2001.
• T. Arai, T. Morita, H.Nagatsuka, Y. Miyamoto, K. Furuya. Fabrication of InP DHBTs with 0.1μm Wide Emitter, 59th Annual Device Research Conference, Vol. III-24, 2001.
• T. Arai, S. Yamagami, Y. Miyamoto, K. Furuya. Submicron Buried Metal Heterojuunction Bipolar Transistors, International Conference on Indium Phosphide and Related Materials, Vol. FA3-7, 2001.
• T. Arai, S. Yamagami, Y. Okuda, Y. Harada, Y. Miyamoto, K. Furuya. InP DHBT with 0.5 um wide emitter along <010> direction toward BM-HBT with narrow emitter, Trans. IECE of Japan, Vol. E84-C, No. 10, pp. 1394, 2001.
• 新井俊希, 山上滋春, 酒井隆史, 宮本恭幸, 古屋一仁. EB露光による微細金属埋込みHBTの作製, 第62回応用物理学会学術講演会, Vol. 13p-ZF-8, 2001.
• L.-E. Wernersson, R. Yamamoto, E. Lind, I. Pietzonka, W. Seifert, Y. Miyamoto, K. Furuya, L. Samuelson. Attractive Potential around a Buried Metallic Gate in a Schottky Collector Hot Electron Transistor, 28th International Symposium on Compound Semiconductors, Mo-P33, 2001.
• 中村弘道, 小口博嗣, 二宮泰徳, 宮本恭幸, 古屋一仁. 80nm周期Au/Ti/n-GaInAs オーミック電極のアイソレーション, 第62回応用物理学会学術講演会, Vol. 14a-YB-10, 2001.
• T. Arai, H. Tobita, Y. Harada, M. Suhara, Y. Miyamoto, K. Furuya. Toward nano-metal buried structure in InP - 20 nm wire and InP buried growth of tungsten, Physica E, Vol. 7, No. 3-4, pp. 896, 2000.
• T. Arai, H. Tobita, Y. Miyamoto, K. Furuya. GaAs buried growth over tungsten stripe using TEG and TMG, J. Crystal Growth, Vol. 221, No. 1-4, pp. 212-219, 2000.
• 栗田昌尚, 宮本恭幸, 古屋一仁. GaInAs/AlAs/InP構造真空エミッタからの電子放出, 第61回応用物理学会学術講演会, Vol. 6p-ZB-12, 2000.
• 山上滋春, 新井俊希, 奥田慶文, 宮本恭幸, 古屋一仁. BMHBT微細化に向けた0.5μｍ幅エミッタInP系DHBTの作製と評価, 第61回応用物理学会学術講演会, Vol. 3p-ZQ-3, 2000.
• 小口博嗣, 佐藤航一郎, 宮本恭幸, 古屋一仁. 電子波干渉素子用GaInAs上80nm周期電極の特性, 第47回応用物理学会関係連合講演会, Vol. 30p-YD-1, 2000.
• 新井俊希, 飛田洋, 宮本恭幸, 古屋一仁. TMGとTEGを材料としたタングステン細線のGaAs OMVPE埋め込み成長, 第47回応用物理学会関係連合講演会, Vol. 31a-P20-10, 2000.
• 新井俊希, 原田恵充, 山上滋春, 宮本恭幸, 古屋一仁. Buried Metal Heterojunction Bipolar Transistorにおけるベースコレクタ間容量の低減, 第47回応用物理学会関係連合講演会, Vol. 28a-ZA-3, 2000.
• Y. Miyamoto, R. Yamamoto, H. Tobita, K. Furuya. Very shallow n-GaAs ohmic contact with 10nm thick GaInAs layer, 19th Electronic Materials Symposium, Vol. B2, 2000.
• T. Arai, S. Yamagami, Y. Okuda, Y. Harada, Y. Miyamoto, K. Furuya. InP DHBT with 0.5μm Wide Emitter along 010 Direction toward BM-HBT with Narrow Emitter, Topical Workshop on Heterostructure Microelectronics (TWHM'00), Vol. Tue-3, 2000.
• Y. Miyamoto, M. Kurita, K. Furuya. Vacuum Microelectronic Electron Emitter by InP Double Barrier Diode Toward RFApplication, 58th Annual Device Research Conference, Vol. III-5, 2000.
• T. Arai, H. Tobita, Y. Miyamoto, K. Furuya. GaAs buried growth over tungsten stripes using TEG and TMG, 11th International Conference on Metalorganic Vapor Phase Epitaxy (ICMOVPE XI), Vol. Tu-A3, 2000.
• T. Arai, Y. Harada, S. Yamagami, Y. Miyamoto, K. Furuya. C_BC reduction in GaInAs/InP buried metal heterojunction bipolar transistor, Twelfth International Conference on Indium Phosphide and Related Materials (IPRM'00), Vol. TuB1.6, 2000.
• YASUYUKI MIYAMOTO. Peak Width Analysis of Current-Voltage Characteristics of Triple-Barrier Resonant Tunneling Diodes, Jpn. J. Appl. Phys, Vol. 39, No. 6A, pp. 3314, 2000.
• T. Arai, Y. Harada, S. Yamagami, Y. Miyamoto, K. Furuya. First Fabrication of GaInAs/InP Buried Metal Heterojunction Bipolar Transistor and Reduction of Base-Collector Capacitance, Jpn. J. Appl. Phys., Vol. 39, No. 6A, pp. L503-L505, 2000.
• Y. Miyamoto, A. Kokubo, H. Oguchi, M. Kurahashi, K. Furuya. Fabrication and transport properties of 50-nm-wide Au/Cr/GaInAs electrode for electron wave interference device, Applied Surface Science, Vol. 159-160, No. 1-4, pp. 179-185, 2000.
• Y.Miyamoto, H.Tobita, K.Oshima, K.Furuya. Barrier thickness dependence of peak current density in GaInAs/AlAs/InP resonant tunneling diodes by MOVPE, Solid State Electronics, Vol. 43, pp. 1395, 1999.
• H.Hongo, Y.Miyamoto, J.Suzuki, M.Suhara, K.Furuya. Wrapped Alignment Mark for fabrication of Interference/Diffraction hot electron devices, Jpn. J. Appl.Phys., Vol. 37, No. 3B, pp. 1518, 1998.
• T.Oobo, R.Takemura, K.Sato, M.Suhara, Y.Miyamoto, K.Furuya. Effect of spacer layer thickness in energy level width narrowing in GaInAs/InP resonant tunneling diodes grown by OMVPE, Jpn. J. Appl. Phys., Vol. 37, No. 2, pp. 445, 1998.
• A.Kokubo, T.Hattori, H.Hongo, M.Suhara, Y.Miyamoto, K.Furuya. 25 nm Pitch GaInAs/InP Buried Structure by Calixarene Resist, Jpn. J. Appl. Phys., Vol. 37, No. 7A, pp. L827, 1998.
• Y.Miyamoto, A.Yamaguchi, K. Oshima, W.Saitoh, M.Asada. Metal-Insulator-Semiconductor emitter with epitaxial CaF2 layer as insnlator, J. Vac. Sci. Technol., Vol. B16, No. 2, pp. 851, 1998.
• Y.Miyamoto, J.Yoshinaga, H.Toda, T.Arai, H.Hongo, T.Hattori, A.Kokubo, K.Furuya. Sub-micron GaInAs/InP Hot Electron Transistors by EBL process and size dependence of current gain, Solid State Electronics, Vol. 42, No. 7-8, pp. 1467, 1998.
• Y.Miyamoto, A.Kokubo, T.Hattori, H.Hongo, M.Suhara, K.Furuya. 25 nm pitch GaInAs/InP buried structure : Improvement by calixarene as EB resist and TBP as P-source in OMVPE regrowth, J. Vac. Sci. Technol. B, Vol. 16, No. 6, pp. 3894-3898, 1998.
• M.Suhara, C.Nagao, H.Honji, Y.Miyamoto, K.Furuya, R.Takemura. Atomically flat OMVPE growth of GaInAs and InP observed by AFM for level narrowing in resonant tunneling diodes, J.Cryst.Growth, Vol. 179, No. 1-2, pp. 18, 1997.
• T.Oobo, R.Takemura, M.Suhara, Y.Miyamoto, K.Furuya. High Peak to Valley Current Ratio GaInAs/GaInP Resonant Tunneling Diodes, Jpn.J.Appl.Phys., Vol. 36, No. 8, pp. 5079, 1997.
• J.M.M.Rios, L.M.Lurardi, S.Chandrasekhar, Y.Miyamoto. A self-consistent method for complete small-signal parameter extraction of InP-based heterojunction bipolar transistors(HBTs), IEEE Transaction of Microwave Theory and Technigue, Vol. 45, No. 1, pp. 39, 1997.
• YASUYUKI MIYAMOTO. High-temperature estimation of phase coherent length of hot electron using GaInAs/InP triple-barrier resonant tunneling diodes grown by OMVPE, Jpn.J.Appl.Phys., Vol. 36, No. 3B, pp. 1846, 1997.
• H.Hongo, H.Tanaka, Y.Miyamoto, T.Otake, J.Yoshinaga, K.Furuya. Electrical properties of 100nm pitch Cr/Au fine electrodes with 40nm width on GaInAs toward hot electron interference/diffraction devices, Microelectronic Engineering, Vol. 35, pp. 241, 1997.
• H.Hongo, Y.Miyamoto, M.Suhara, K.Furuya. Hot electron interference by 40nm-pitch double slit buried in semiconductor, Microelectronic Engineering, Vol. 35, pp. 337, 1997.
• H.Hongo, Y.Miyamoto, M.Suhara, K.Furuya. A 40nm pitch doble slit experiment of hot electrons in a semiconductor under a magnetic field, Applied Physics Letter, Vol. 70, No. 1, pp. 93, 1997.
• H.Hongo, Y.Miyamoto, M.Gault, K.Furuya. Influence of finite energy width in electron distribution to an experiment of hot electron donble-slit eyperiment, J. Appl. Phys., Vol. 82, No. 8, pp. 3846, 1997.
• MASAHIRO WATANABE, H. Hongo, T. Hattori, Y. Miyamoto, K. Furuya, T. Matsunuma, M. Asada. Seventy nm Pitch Patternings on CaF₂ by e-beam Exposure: An Inorganic Resist and a Contamination Resist, Jpn. J. Appl. Phys., Vol. 35, No. 12A, pp. 6342-6343, Dec. 1996.
• MASAHIRO WATANABE, Y. Miyamoto, K, T. Maruyama, M. Asada. Detection of hot electron current with scanning hot electron microscopy, Appl. Phys. Lett, Vol. 69, No. 15, pp. 2196-2198, Oct. 1996.
• Y.Miyamoto, J.M.M.Rios, A.G.Dentai, S.Chandrasekhar. Reduction of Base-Collector Capacitance by Undercut of Collector and Subcollector in GaInAs/InP DHBTS, IEEE Electron Devices Letter, Vol. 17, No. 3, pp. 97, 1996.
• H.Hongo, H.Tanaka, Y.Miyamoto, J.Yoshinaga, K.Furuya. Electrical properties of 100nm pitch Cr/Au fine electrodes with 40nm width on GaAs, Japanese Journal of Applied Physics, Vol. 35, No. 8A, pp. L964, 1996.
• H.Hongo, T.Hattori, Y.Miyamoto, K.Furuya, K.Matsunuma, M.Watanabe, M.Asada. Seventy nm pitch patterning on CaF2 by e-beam exposure : An inorganic resist and a contamination resist, Japanese Journal of Applied Physics, Vol. 35, No. 12A, pp. 6342, 1996.
• Y.Miyamoto, A.G.Dentai, J.M.M.Rios, S.Chandrasekhar. GaInAs/InP DHBT Incorporating Thick Extrinsic Base and Seletively Regrown Emitter, Electronics Letter, Vol. 31, No. 17, pp. 1510, 1995.
• H.Hongo, J.Suzuki, M.Suhara, Y.Miyamoto, K.Furuya. Nanostructure Alignment for Hot Electron Interferenc/Diffraction Devices, Japanese Journal Applied Physics, Vol. 34, No. 8B, pp. 4436, 1995.
• H.Hongo, Y.Miyamoto, J.Suzuki, M.Funayama, T.Morita, K.Furuya. Ultrafine fabrication technique for hot electron interference/diffraction devices, Japanese Journal Applied Physics, Vol. 33, No. 1B, pp. 925-928, 1994.
• M.Suhara, Y.Miyamoto, H.Hongo, J.Suzuki, K.Furuya. GaInAs/InP organometallic vapor phase epitaxy regrowth for ultrafine buried heterostructure with 50nm pitch toward electron wave devices, Journal of Crystal Growth, Vol. 145, No. 1-4, pp. 698-701, 1994.
• T.Sekiguchi, Y.Miyamoto, K.Furuya. Influence of impurities on the performance of doped well Ga In As/Inp resonant tunneling diode, Jpn. J. Appl. Phys, Vol. 32, No. 2B, pp. L243-L246, 1993.
• Y.Miyake, H.Hirayama, K.Kudo, S.Tamura, S.Arai, M.Asada, Y.Miyamoto, Y.Suematsu. Room temperature operation of GaInAs/GaInAsP/InP SCH lasers with quantuw-wire size active region, IEEE J. Quantum Electron, Vol. 29, No. 6, pp. 2123-2133, 1993.
• YASUYUKI MIYAMOTO. Fabrication technology for long-wavelength Ga In As(P)InP quantum-wire lasers by wet-chemical etching and OMVPE regrowth, Opto electronics-Devices and technology, Vol. 8, No. 4, pp. 461-478, 1993.
• K.Kurihara, Y.Miyamoto, K.Furuya. Observation of InP Surfaces after (NH4)2Sx treatment by a scanning tunneling microscope, Jpn. J. Appl. Phys, Vol. 32, No. 3B, pp. L444, 1993.
• Y.Miyamoto, K.Furuya, D.Yamazaki. Fabricution of ultrafine X-ray mask using pricise crystal growth techniqe, Jpn. J. Appl. Phys., Vol. 31, No. 4A, pp. L432, 1992.
• T.Suemasu, Y.Miyamoto, K.Furuya. Improvement of regrown interface in InP organo-metallic vapor phase epitaxy, Jpn. J. Appl. Phys., Vol. 30, No. 4B, pp. L1702, 1991.
• YASUYUKI MIYAMOTO. Fabrication of quantum wire structure, Journal of crystallgraphic society of Japan, Vol. 33, No. 3, pp. 141, 1991.
• T.Yamamoto, Y.Miyamoto, M.Ogawa, E.Inamura, K.Furuya. Buried rectangnber GaInAs/InP corrugations of 70nm pitch by OMVPE, Electronics Lett., Vol. 26, No. 13, pp. 875, 1990.
• Y.Miyamoto, S.Yamaura, K.Furuya. Negative differential conductiance due to resonant states in GmInAs/InP hot electron transistors, Appl. Phys. Lett, Vol. 57, No. 20, pp. 2104, 1990.
• S.Yamaura, Y.Miyamoto, K.Furuya. High current gain GnInAS/InP hot electron transistor, Electronics Lett., Vol. 26, No. 14, pp. 1055, 1990.
• Y.Miyamoto, Y.Miyake, M.Asada, Y.Suematsu. Threshold current density of GaInAsP/InP quantum box Lasers, IEEE J. Quantum. Electron, Vol. QE25, No. 9, pp. 2001, 1989.
• E.Inamura, Y.Miyamoto, S.Tamura, S.Takasugi, K.Furuya. Wet chemical etching for ultra fine periodic structrures ; rectangular InP corrugations of 70nm pitch and 100nm depth, Jpn. J. Appl. Phys., Vol. 28, No. 10, pp. 2193, 1989.
• Y.Miyamoto, C.Watanabe, M.Nagashima, K.Furuya, Y.Suematsu. Fabrication of GaInAsP/InP heterostructure for 1.5μm lasers by OMVPE, Trans. IEICE of Japan., Vol. E-70, No. 2, pp. 121, 1987.
• Y.Miyamoto, M.Cao, Y.Shingai, K.Furuya, Y.Suematsu, K.G.Ravikumar, S.Arai. Ligth emisson form quantun box structure by current injection, Jpn. J. Appl. Phys, Vol. 26, No. 4, pp. L225, 1987.

Book

• Tomohiro Amemiya, Toru Kanazawa, Atsushi Ishikawa, Nobuhiko Nishiyama, Yasuyuki Miyamoto, Takuo Tanaka, Shigehisa Arai. Permeability Engineering of Semiconductor Photonic Devices, Interferometers: Fundamentals, Methods and Applications (ISBN: 978-1-63483-692-0), Nova Science Publishers, pp. 15-36, 2015.
• 芝原 健太郎, YASUYUKI MIYAMOTO, Ken Uchida. タウア・ニン 最新VLSIの基礎 第二版, 丸善, Jan. 2013.
• YASUYUKI MIYAMOTO. グリーンナノテクノロジー―環境・エネルギー問題に挑戦する人々, 日刊工業新聞社, Feb. 2011.
• YASUYUKI MIYAMOTO. 電子デバイス, 培風館, Feb. 2009.
• YASUYUKI MIYAMOTO. タウア・ニン　最新VLSIの基礎　(共訳), 丸善, 丸善, 2002.
• YASUYUKI MIYAMOTO. Semiconductor Lasers and Photonic Integrated Circuits, Chapman & Hall, Chapman & Hall, 1994.

International Conference (Reviewed)

• Y. Miyamoto, N. Nishiyama, S. Suzuki. Electron beam lithography in processes for electron/opto/teraherz devices, 35th International Microprocesses and Nanotechnology Conference, Nov. 2023.
• K. Makiyama, S. Yoshida, K. Nakata, Y. Miyamoto. Innovative RF Device Technologies for Advanced Information and Communications Network Society, IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, Oct. 2022.
• Y. Ito, S. Tamai, T. Hoshi, Y. Miyamoto. GaN channel thickness dependence in AlGaN / GaN HEMT structures with back barriers, 2022 International Conference on Solid State Devices and Materials, Sept. 2022.
• T. Gotow, T. Arai, T. Aota, Y. Miyamoto. Evaluation of TMAH treatment for isolation process of N-polar GaN HEMTs, Compound Semiconductor Week, June 2022.
• Tomimasa Go, M. Kitamura, T. Gotow, Y. Miyamoto. PMA Evaluation of TiN ALD in InGaAs Nanosheet MOSFETs, International Microprocesses and Nanotechnology Conference, Oct. 2021.
• T. Gotow, Tatsushi Suka, Y. Miyamoto. Comparative study of breakdown and interface properties of gate insulator on N-polar and Ga-polar GaN MIS capacitor, International Conference on Solid State Devices and Materials, Sept. 2021.  Official location  
• Y. Miyamoto, T. Gotow. Proposal of breakdown voltage control of GaN HEMT by interface charge, Compound Semiconductor Week 2021, May 2021.  Official location  
• Tomoya Aota, Akihiro Hayasaka, isao makabe, Shigeki Yoshida, Takahiro Gotow, YASUYUKI MIYAMOTO. Wet Etching for Isolation of N-polar GaN HEMT Structure by Electrodeless Photo-Assisted Electrochemical Reaction, 33rd International Microprocesses and Nanotechnology Conference (MNC 2020), Nov. 2020.
• Moataz Eissa, Takuya Mitarai, Tomohiro Amemiya, Nobuhiko Nishiyama, Yasuyuki Miyamoto. Fabrication of Si Photonics Waveguides by Thick Resist-Mask Electron Beam Lithography Proximity Effect Correction, 32nd International Microprocesses and Nanotechnology Conference (MNC 2019), Oct. 2019.
• K. Fukuda, N. Nogami, S. Kunisada, Y. Miyamoto. Circuit speedoriented device design scheme for double gate hetero tunnel FETs, 2019 International Conference on Solid State Devices and Materials(SSDM 2019), PS-1-21(LN),, Sept. 2019.
• M.Kitamura, T.Kanazawa, Y.Miyamoto. Evaluation of fabricationmethod of InGaAs nanosheet, 13rd th Topical Workshop onHeterostructure Microelectronics, (TWHM 2019), 6-6, Aug. 2019.
• Tomohiro Amemiya, Tomoya Yoshida, Yuki Atsumi, Yasuyuki Miyamoto, Yoichi Sakakibara, Shigehisa Arai. Si-based Orbital Angular Momentum Mux/Demux Module, IEEE International Nanoelectronics Conference (INEC 2019), July 2019.
• Y. Miyamoto. Simulation of the Short Channel Effect in GaN HEMT with a Combined Thin Undoped Channel and Semi-Insulating Layer, Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD 2019), B7-4, July 2019.
• A. Hayasaka, R. Aonuma, K. Hotta, I. Makabe, S. Yoshida, Y. Miyamoto. N-polar GaN HEMT with Al2O3 gate insulator, Compound Semiconductor Week 2019, MoP-G-8 (Poster), May 2019.
• Tomohiro Amemiya, Tomoya Yoshida, Yuki Atsumi, Nobuhiko Nishiyama, Yasuyuki Miyamoto, Yoichi Sakakibara, Shigehisa Arai. Orbital Angular Momentum Mux/Demux Module Using Vertically Curved Si Waveguides, 2019 Optical Fiber Communication Conference (OFC 2019), Mar. 2019.
• Y. Miyamoto, N. Kise, R. Aonuma. GaAsSb/InGaAs double gate tunnel FET operating below 60 mv/decade and temperature dependence of band-edge decay parameters, 2018 Workshop on Innovative Nanoscale Devices and Systems (WINDS), P7, Nov. 2018.
• Y. Miyamoto. Prospective New Fuctionality of Monolithic GaN HEMT Integrated Circuits, 4th Intensive Discussion on Growth of Nitride Semiconductors (IDGN-4), ED-III-1, Nov. 2018.
• K. Hotta, Y. Tomizuka, K. Itagaki, I. Makabe, S. Yoshida, Y. Miyamoto. Annealing temperature dependence of alloy contact for N-polar GaN HEMT structure, International Workshop on Nitride Semiconductors (IWN 2018), Nov. 2018.
• Y. Higa, M. Yoshida, N. Nishiyama, Y. Miyamoto, Nobuyuki Kagi. High Power, 14xx-nm Eye-safe, Epitaxially Stacked Pulse Laser for Detection and Ranging Applications, 2018 IEEE International Semiconductor Laser Conference (ISLC), WC7, Sept. 2018.
• R. Aonuma, N. Kise, Y. Miyamoto. Improvement in GaAsSb/InGaAs double-gate tunnel FET using thermal evaporation for gate electrode and Al2O3/ZrO2 for gate insulator, 2018 International Conference on Solid State Devices and Materials (SSDM 2018), PS-1-14, Sept. 2018.
• W. Zhang, S. Netsu, T.Kanazawa, T. Amemiya, Y. Miyamoto. p-MoS2/HfS2 van der Waals Heterostructure Transistor Using Ni Backgate Buried in HfO2 Dielectric, 2018 International Conference on Solid State Devices and Materials (SSDM 2018), M-7-03, Sept. 2018.
• D. Nakajun, N. Kanai, R. F. T. Fathulah, H. Fujita, E. Yagyu, Y. Miyamoto. Multi-level inverter toward GaN HEMT monolithic integrated circuit, Les Eastman Conference 2018, IIIB-5, Aug. 2018.
• Nanae Kanai, Kenichi Okada, Yasuyuki Miyamoto. Investigation of Active Load Matching Using GaN HEMT as Digital Switch, Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD), July 2018.
• Y.Miyamoto, T. Kanazawa, N. Kise, H. Kinoshita, Kazuto Ohsawa. Regrown Source / Drain in InGaAs Multi-Gate MOSFET, 19th International Conference on Metalorganic Vapor Phase Epitaxy (ICMOVPE-XIX), P2-32, June 2018.
• Toru Kanazawa, Kazuto Ohsawa, Tomohiro Amemiya, Nobukazu Kise, Ryosuke Aonuma, Yasuyuki Miyamoto. Fabrication of InGaAs Nanosheet Transistors with Regrown Source, Compound Semiconductor Week (CSW2018), We3C3.2, May 2018.
• K. Makiyama, T. Ohki, S. Ozaki, Y. Niida, N. Okamoto, Y. Minoura, M. Sato, Y. Kamada, T. Ishiguro, K. Joshin, N. Nakamura, Y. Miyamoto. InAlGaN/GaN-HEMT Device Technologies for High-Power-Density W-band Amplifiers (Invited), International Conference on Materials and Systems for Sustainability 2017 (ICMaSS2017 ), 30-Nitride-3, Sept. 2017.
• Seiko Netsu, Toru Kanazawa, Vikrant Upadhyaya, Teerayut Uwanno, Tomohiro Amemiya, Kosuke Nagashio, Yasuyuki Miyamoto. Type II HfS2/MoS2 heterojunction Tunnel FET, 12th Topical Workshop on Heterostructure Microelectronics (TWHM 2017), No. 6-3, Aug. 2017.
• D. Nakajun, R. F. T. Fathulah, H. Fujita, E. Yagyu, Y. Miyamoto. Multi-level inverter by GaN HEMT on semi-insulating substrate, 12th Topical Workshop on Heterostructure Microelectronics (TWHM 2017), 4-4, Aug. 2017.
• K. Makiyama, S. Ozaki, Y. Niida, T. Ohki, N. Okamoto, Y. Minoura, M. Sato, Yoichi Kamada, K. Joshin, N. Nakamura, Yasuyuki Miyamoto. Advanced HEMTs and MMICs Technologies for Next Generation Millimeter-wave Amplifiers (Invited), 12th International Conference on Nitride Semiconductor (ICNS), C1,1, July 2017.
• Y. Miyamoto, D. Nakajun, R. F. T. Fathulah, H. Fujita, E. Yagyu. High speed GaN HEMT for power electronics (Invited), 12th International Conference on Nitride Semiconductor (ICNS), C5.1, July 2017.
• N. Kise, S. Iwata, R. Aonuma, K. Ohsawa, Y. Miyamoto. GaAsSb/InGaAs Double-Gate Vertical Tunnel FET with a Subthreshold Swing of 68mV/dec at Room Temperature, Compound Semiconductor Week 2017, C804, May 2017.
• K. Makiyama, Y. Niida, S. Ozaki, T. Ohki, N. Okamoto, Y. Minoura, M. Sato, Y. Kamada, K. Joshin, K. Watanabe, Y. Miyamoto. GaN HEMT Device Technology for W-band Power Amplifiers (Invited), Compound Semiconductor Week 2017, A6-1, May 2017.
• K. Makiyama, Y. Niida, S. Ozaki, T. Ohki, N. Okamoto, Y. Minoura, M. Sato, Y. Kamada, K. Joshin, K. Watanabe, Y. Miyamoto. High-Power-Density InAlGaN/GaN-HEMT Technology for W-Band Amplifier (Invited), 2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), Oct. 2016.
• K. Ohsawa, N. Kise, Y. Miyamoto. Deposition Temperature and Al2O3 Thickness Dependence on the Mobility of HfO2/Al2O3/InGaAs Gate Stacks, 2016 International Conference on Solid State Devices and Materials (SSDM), Sept. 2016.
• M. Kashiwano, A. Yukimachi, Y. Miyamoto. Experimental approach for feasibility of superlattice FETs, 2016 Lester Eastman Conference (LEC), pp. 8-11, Aug. 2016.  Official location  
• K. Makiyama, S. Ozaki, Y. Niida, T. Ohki, N. Okamoto, Y. Minoura, M. Sato, Y. Kamada, K. Joshin, K. Watanabe, Y. Miyamoto. InAlGaN/GaN-HEMT device technologies for W-band high-power amplifier (Invited), 2016 Lester Eastman Conference (LEC), pp. 31-34, Aug. 2016.  Official location  
• K. Makiyama, S. Ozaki, T. Ohki, N. Okamoto, Y. Minoura, Y. Niida, Y. Kamada, M. Sato, K. Joshin, K. Watanabe, Y. Miyamoto. High-Performance GaN-HEMT Technology for W-band Amplifier (Invited), URSI AP-RASC 2016, Aug. 2016.
• Toru Kanazawa, Tomohiro Amemiya, Vikrant Upadhyaya, Atsushi Ishikawa, Kenji Tsuruta, Takuo Tanaka, Yasuyuki Miyamoto. Effect of the HfO2 passivation on HfS2 Transistors, 16th International Conference on Nanotechnology (IEEE NANO 2016), No. ThAM11.3, Aug. 2016.
• Y. Miyamoto, W. Lin, S.Iwata, K. Fukuda. Steep sub-threshold slope in short-channel InGaAs TFET (Invited), The 18th International Symposium on the Physics of Semiconductors and Applications (ISPSA-2016), A6-I-01, July 2016.
• Vikrant Upadhyaya, Toru Kanazawa, YASUYUKI MIYAMOTO. Vacuum annealing and passivation of Hf₂ FET for mitigation of atmospheric degradation, 2016 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD2016), A5-7, pp. 231-235, July 2016.
• Tomohiro Amemiya, Toru Kanazawa, Atsushi Ishikawa, Nobuhiko Nishiyama, Yasuyuki Miyamoto, Tatsuhiro Urakami, Takuo Tanaka, Shigehisa Arai. (Invited) Permeability Engineering in Optical Communication Devices, The First A3 Metamaterials Forum, I-25, July 2016.
• Haruki Kinoshita, Nobukazu Kise, Atsushi Yukimachi, Toru Kanazawa, Yasuyuki Miyamoto. Operation of 16-nm InGaAs channel multi-gate MOSFETs with regrown source/drain, Compound Semiconductor Week (CSW2016), TuD4-2, June 2016.
• K. Makiyama, S. Ozaki, T. Ohki, N. Okamoto, Y. Minoura, Y. Niida, Y. Kamada, K. Joshin, K. Watanabe, Y. Miyamoto. Collapse Free High Power InAlGaN/GaN-HEMT with 3 W/mm at 96 GHz, 2015 IEEE International Electron Devices Meeting (IEDM), Dec. 2015.
• Toru Kanazawa, Tomohiro Amemiya, Atsushi Ishikawa, Vikrant Upadhyaya, Takuo Tanaka, Kenji Tsuruta, Yasuyuki Miyamoto. HfS2 Electric Double Layer Transistor with High Drain Current, 47th International Conference on Solid State Devices and Materials (SSDM 2015), Sept. 2015.
• S. Iwata, W. Lin, K. Fukuda, Y. Miyamoto. Design of drain for low off current in GaAsSb/InGaAs tunnel FETs, 2015 International Conference on Solid State Devices and Materials (SSDM), Sept. 2015.
• H.Kinoshita, S.Netsu, Y.mishima, T.Kanazawa, Y.Miyamoto. Fabrication of InGaAs channel multi-gate MOSFETs with MOVPE regrown source/drain, 11th Topical Workshop on Heterostructure Microelectronics (TWHM 2015), Aug. 2015.
• K. Ohsawa, Y. Mishima, Y. Miyamoto. Operation of 13-nm channel length InGaAs-MOSFET with n-InP source, 27th International Conference on Indium Phosphide and Related Materials, July 2015.
• S. Netsu, T. Kanazawa, Y. Miyamoto. Improvement of Interface Property of HfO2/Al2O3/In0.53Ga0.47As Using Nitrogen Plasma Cleaning and Hydrogen Annealing, 27th International Conference on Indium Phosphide and Related Materials, July 2015.
• Tomohiro Amemiya, Atsushi Ishikawa, Toru Kanazawa, Nobuhiko Nishiyama, Yasuyuki Miyamoto, Takuo Tanaka, Shigehisa Arai. (Invited) Possibility of permeability control on InP-based photonic integration platform, 8th International Conference on Materiaals for Advanced Tachnologies (ICMAT 2015), No. D2-PM2, June 2015.
• T. Kanazawa, T. Amemiya, A. Ishikawa, V. Upadhyaya, K. Tsuruta, T. Tanaka, Y. Miyamoto. Fabrication of Thin-Film HfS2 FET, 73rd Device Research Conference (DRC), June 2015.
• R. Yamanaka, T. Kanazawa, E. Yagyu, Y. Miyamoto. Normally-off AlGaN/GaN HEMT using Digital Etching Technique, 2014 International Microprocesses and Nanotechnology Conference (MNC), Nov. 2014.
• K. Ohashi, M. Fujimatsu, Y. Miyamoto. Body width dependence of subthreshold slope and on-current in GaAsSb/InGaAs Double Gate Vertical Tunnel FETs, 2014 International Conference on Solid State Devices and Materials (SSDM), Sept. 2014.
• Tomohiro Amemiya, Toru Kanazawa, Atsushi Ishikawa, JoonHyun Kang, Nobuhiko Nishiyama, YASUYUKI MIYAMOTO, Takuo Tanaka, SHIGEHISA ARAI. (Invited) Meta-photonics for Advanced InP-based Photonic Integration, the Collaborative Conference on Materials Research (CCMR) 2014, No. Day1. p.85, June 2014.
• Y. Mishima, T. Kanazawa, H. Kinoshita, E. Uehara, Y. Miyamoto. InGaAs tri-gate MOSFETs with MOVPE regrown source/drain, 72nd Device Research Conference (DRC), June 2014.
• T. Irisawa, M. Oda, K. Ikeda, Y. Moriyama, E. Mieda, W. Jevasuwan, T. Maeda, O. Ichikawa, T. Osada, M. Hata, Y. Miyamoto, T. Tezuka. High Electron Mobility Triangular InGaAs-OI nMOSFETs with (111)B Side Surfaces Formed by MOVPE Growth on Narrow Fin Structures, 2013 International Electron Devices Meeting, Dec. 2013.
• Yuki Atsumi, N. Taksatorn, N. Nishiyama, Y. Miyamoto, S.Arai. Miniaturization of exposure area for electron beam lithography using proximity effect correction toward Si optical circuits, 26th International Microprocesses and Nanotechnology Conference (MNC 2013), Nov. 2013.
• Tomohiro Amemiya, Toru Kanazawa, Atsushi Ishikawa, Seiji Myoga, JoonHyun Kang, Nobuhiko Nishiyama, YASUYUKI MIYAMOTO, Takuo Tanaka, SHIGEHISA ARAI. (Invited) Photonic metamaterials in semiconductor optical devices, 2013 EMN Open Access Week, Oct. 2013.
• K. Ohsawa, A. Kato, T. Sagai, T. Kanazawa, E. Uehara, Y. Miyamoto. Channel thickness dependence on InGaAs MOSFET with n-InP source for high current density, 10th Topical Workshop on Heterostructure Microelectronics (TWHM 2013), 2-9, pp. 19-20, Sept. 2013.
• M. Kashiwano, A. Yukimachi, Y. Miyamoto. Dependence of the Carrier Concentration in InGaAs/InP Superlattice-based FETs with a Steep Subthreshold Slope, 2013 International Conference on Solid State Devices and Materials (SSDM), Sept. 2013.
• Y. Yamaguchi, K. Hayashi, T. Oishi, H. Otsuka, K. Yamanaka, Y. Miyamoto. Analysis on trade-off between drain resistance and drain-source capacitance of source field plate GaN HEMT, 2013 International Conference on Solid State Devices and Materials (SSDM), Sept. 2013.
• M. Oda, T. Irisawa, E. Mieda, Y. Kurashima, H. Takagi, W. Jevasuwan, T. Maeda, O. Ichikawa, T. Ishihara, T. Osada, Y. Miyamoto, T. Tezuka. Suppression of short channel effects in accumulation-type UTB-InGaAs-OI nMISFETs with raised S/D fabricated by gate-last process, 2013 International Conference on Solid State Devices and Materials (SSDM), Sept. 2013.
• Tomohiro Amemiya, Toru Kanazawa, Atsushi Ishikawa, Seiji Myoga, Eijun Murai, Takahiko Shindo, J. Kang, Nobuhiko Nishiyama, Yasuyuki Miyamoto, Takuo Tanaka, Shigehisa Arai. Electrically-driven Permeability-controlled Optical Modulator using Mach-Zehnder Interferometer with Metamaterial, The Conference on Lasers and Electro-Optics 2013 (CLEO 2013), No. QM1A.6, June 2013.  Official location  
• A. Kato, T. Kanazawa, Eiji Uehara, Y. Yonai, Y. Miyamoto. Sub-50-nm InGaAs MOSFET with n-InP source on Si substrate, 25th Int. Conf. Indium Phosphide and Related Materials (IPRM2013), May 2013.
• Tomohiro Amemiya, Toru Kanazawa, Atsushi Ishikawa, Seiji Myoga, Eijun Murai, Takahiko Shindo, J. Kang, Nobuhiko Nishiyama, Yasuyuki Miyamoto, Takuo Tanaka, Shigehisa Arai. Permeability-controlled Optical Modulator with Tri-gate Metamaterial, the 4th International Topical Meeting on Nanophotonics and Metamaterials (NANOMETA 2013), No. FRI5o.2, Jan. 2013.
• Y. Yamaguchi, K. Hayashi, T. Oishi, H. Otsuka, T. Nanjo, K. Yamanaka, M. Nakayama, Y. Miyamoto. Simulation study and reduction of reverse gate leakage current for GaN HEMTs, Oct. 2012.
• M. Kashiwano, J. Hirai, S. Ikeda, M. Fujimatsu, Y. Miyamoto. High Open Circuit Voltage Gain in Vertical InGaAs Channel Metal-Insulator-Semiconductor Field-Effect Transistor using Heavily Doped Drain Region and Narrow Channel Mesa, 2012 International Conference on. Solid State Devices and Materials (SSDM 2012), Sept. 2012.
• T. Oishi, K. Hayashi, Y. Yamaguchi, H. Otsuka, K. Yamanaka, M. Nakayama, Y. Miyamoto. Mechanism study of gate leakage current for AlGaN/GaN HEMT structure under high reverse bias by TSB model and TCAD simulation, 2012 International Conference on. Solid State Devices and Materials (SSDM 2012), Sept. 2012.
• Y. Yamaguchi, K. Hayashi, T. Oishi, H. Otsuka, K. Yamanaka, M. Nakayama, Y. Miyamoto. Analysis on trade-off between electric field and gate-drain capacitance for GaN HEMT by T-CAD simulation, 2012 International Conference on. Solid State Devices and Materials (SSDM 2012), Sept. 2012.
• M. Fujimatsu, H. Saito, Y. Miyamoto. 71 mV/dec of Sub-Threshold Slope in Vertical Tunnel Field-Effect Transistors with GaAsSb/InGaAs Heterostructure, 24th Int. Conf. Indium Phosphide and Related Materials (IPRM2012), Aug. 2012.
• K. Tanaka, Y. Miyamoto. InP HBT with 55-nm-wide Emitter and Relationship between Emitter Width and Current Density, 24th Int. Conf. Indium Phosphide and Related Materials (IPRM2012), Aug. 2012.
• Jun Hirai, Tomoki Kususaki, Shunsuke Ikeda, YASUYUKI MIYAMOTO. Vertical InGaAs MOSFET with HfO2 gate, 2012 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices(AWAD 2012), 2012.
• YASUYUKI MIYAMOTO, Hisashi Saito, Toru Kanazawa. High-current-density InP ultrafine devices for high-speed operation, The International Conference on Infrared, Millimeter, and Terahertz Waves (IRMMW-THz), Oct. 2011.
• T. Kanazawa, R. Terao, S. Ikeda, Y. Miyamoto. MOVPE-regrown source/drain regions for III-V MOSFETs with high drain current of 1.28 A/mm, 23rd Int. Conf. Indium Phosphide and Related Materials (IPRM2011), Sept. 2011.  Official location  
• N. Takebe, Y. Miyamoto. Reduction of Base-Collector Capacitance in InP/InGaAs DHBT with Buried SiO2 Wires, 2011 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices（AWAD), Sept. 2011.  Official location  
• A. Kato, T. Kanazawa, S. Ikeda, Y. Yonai, YASUYUKI MIYAMOTO. Reduction of Access Resistance of InP/InGaAs Composite-Channel MOSFET with A Back Source Electrode, 2011 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices（AWAD), Sept. 2011.  Official location  
• Y. Yamaguchi, T. Sagai, Y. Miyamoto. Fabrication of InP/InGaAs SHBT on Si Substrate by Using Transferred Substrate Process, 9th Topical Workshop on Heterostructure Materials, Sept. 2011.  Official location  
• Motohiko Fujimatsu, Hisashi Saito, YASUYUKI MIYAMOTO. GaAsSb/InGaAs vertical tunnel FET with a 25 nm-wide channel mesa structure, 2011 International Conference on Solid State Devices and Materials(SSDM 2011), 2011.
• Yosiharu Yonai, Toru Kanazawa, Shunsuke Ikeda, YASUYUKI MIYAMOTO. High Drain Current (>2A/mm) InGaAs channel MOSFET at VD=0.5V with Shrinkage of Channel Length by InP Anisotropic Etching, 2011 IEEE International Electron Devices Meeting (IEDM 2011), 2011.
• Matsumoto, Y., Saito, H., YASUYUKI MIYAMOTO. Reduction of source parasitic capacitance in vertical InGaAs MISFET, Conference Proceedings - International Conference on Indium Phosphide and Related Materials, 2011.
• Chien-I Kuo, Wee Chin Lim, Heng-Tung Hsu, Chin-Te Wang, Li-Han Hsu, Faiz Aizad, Guo-Wei Hung, Yasuyuki Miyamoto, Edward Yi Chang. Bonding Temperature Effect on the Performance of Flip Chip Assembled 150nm mHEMT Device on Organic Substrate, 2010 International Conference on Enabling Science and Nanotechnology (ESciNano), Dec. 2010.
• Toru Kanazawa, Ryousuke Terao, Yuutarou Yamaguchi, Shunsuke Ikeda, Yosiharu Yonai, YASUYUKI MIYAMOTO. InP/InGaAs MOSFET with Back-Electrode Structure Bonded on Si Substrate Using a BCB Adhesive Layer, 2010 International Conference on Solid State Devices and Materials, pp. 129-130, Sept. 2010.
• T. Kanazawa, K. Wakabayashi, H. Saito, R. Terao, T. Tajima, S. Ikeda, Y. Miyamoto, K. Furuya. Submicron InP/InGaAs composite channel MOSFETs with selectively regrown n+-source/drain buried in channel undercut, 22nd Int. Conf. Indium Phosphide and Related Materials, June 2010.
• Y. Miyamoto, T. Kanazawa, H. Saito. InGaAs MISFET with epitaxially grown source, The 3rd International Symposium on Organic and Inorganic Electronic Materials and Related Nanotechnologies, InGaAs MISFET with epitaxially grown source, June 2010.
• H. Saito, Y. Miyamoto, K. Furuya. Vertical InGaAs FET with hetero-launcher and undoped channel, 22nd Int. Conf. Indium Phosphide and Related Materials, June 2010.
• C.-T. Wang, C.-I. Kuo, W.-C. Lim, L.-H. Hsu, H.-T. Hsu, Y. Miyamoto, E.Y. Chang, S.-P. Tsai, Y.-S. Chiu. An 80 nm In0.7Ga0.3As MHEMT with Flip-Chip Packaging for W-Band Low Noise Applications, 22nd Int. Conf. Indium Phosphide and Related Materials, June 2010.
• Faiz Aizad, Heng-Tung Hsu, Chien-I Kuo, Chien-Ying Wu, Edward Yi Chang, Yasuyuki Miyamoto, Guo-Wei Huang, Yu-Lin Chen, Yu-Sheng Chiu. Investigation Logic Performances of 80-nm HEMTs for InxGa1?xAs, 37th International Symposium on Compound Semiconductor, June 2010.
• M. Yamada, T. Uesawa, Y. Miyamoto, K. Furuya. Deviation from Proportional Relationship between Emitter Charging Time and Inverse Current of Heterojunction Bipolar Transistors Operating at High Current Density, 37th International Symposium on Compound Semiconductor, June 2010.
• YASUYUKI MIYAMOTO. Vertical InGaAs FET with hetero-launcher and undoped channel, International Symposium on Advanced Nanodevices and Nanotechnology (ISANN), Dec. 2009.
• Toru Kanazawa, Hisashi Saito, Kazuya Wakabayashi, Ryousuke Terao, Tomonori Tajima, YASUYUKI MIYAMOTO, KAZUHITO FURUYA. Fabrication of InP/InGaAs Undoped Channel MOSFET with Selectively Regrown N⁺-InGaAs Source Region, 2009 International Conference on Solid State Devices and Materials, pp. 246-247, Oct. 2009.
• Takafumi Uesawa, Masayuki Yamada, YASUYUKI MIYAMOTO, KAZUHITO FURUYA. Monte Carlo Analysis of Base Transit Times of InP/Gaines Heterojunction Bipolar Transistors with Ultrathin Bases, Topical Workshop on Heterostructure Materials (TWHM2009), Aug. 2009.
• YASUYUKI MIYAMOTO, Hiroaki Yamashita, Naoaki Takebe, KAZUHITO FURUYA. In-situ Etching in MOVPE for Thin Collector of InP HBT with Buried SiO2 Wire, Topical Workshop on Heterostructure Materials (TWHM2009), Aug. 2009.
• YASUYUKI MIYAMOTO, Shinnosuke Takahashi, Takashi Kobayashi, Hiroyuki Suzuki, KAZUHITO FURUYA. Evaluation of collector current spreading of InGaAs SHBT with 75-nm-thick collector, 2009 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices（AWAD）, June 2009.
• Toru Kanazawa, KAZUHITO FURUYA, YASUYUKI MIYAMOTO, Hisashi Saito, kazuya wakabayashi, Tomonori Tajima. InP/InGaAs-channel MOSFET with MOVPE Selective Regrown Source, IEEE 21th Conference on Indium Phosphide and Related Materials, May 2009.
• Chien-I Kuo, Heng-Tung Hsu, Chung Li, Chien Ying Wu, Edward Yi Chang, YASUYUKI MIYAMOTO, Y.-L. Chen, D. Biswas. A 40-nm-Gate InAs/InGaAs Composite-Channel HEMT with 2200 mS/mm and 500-GHz fT, IEEE 21th Conference on Indium Phosphide and Related Materials (IPRM'09), May 2009.
• H. Saito, Y. Miyamoto, K. Furuya. Vertical InGaAs MOSFET with Hetero-Launcher and Undoped Channel, IEEE 21th Conference on Indium Phosphide and Related Materials, 311, May 2009.
• Edward Yi Chang, Chien-I Kuo, Heng-Tung Hsu, YASUYUKI MIYAMOTO, Chia Ta Chang, Chien Ying Wu. Evaluation of InAs QWFET for Low Power Logic applications, Semiconductor Technologies meeting,ECS Transactions Vol. 12, 7th ISTC/CISC Emerging, Mar. 2009.
• YASUYUKI MIYAMOTO. InGaAs MISFET with hetero-laucher, 2009 RCIQE International Seminar on "Advanced Semiconductor Materials and Devices", Mar. 2009.
• Yasuyuki Miyamoto, Takashi Hasegawa, Hisashi Saito, Kazuhito Furuya. RF Characteristics of Schottky-Gate-Controlled Hot Electron Transistor, IEEE Nanotechnology Materials and Devices Conference 2008, Oct. 2008.
• T. Kanazawa, H. Saito, K. Wakabayashi, Y. Miyamoto, K. Furuya. Lateral Buried Growth of N+-InGaAs Source/Drain Region to Undercut InGaAs Channel Structure for High Drive Current N-type MOSFET, 2008 International Conference on Solid State Devices and Materials, Sept. 2008.
• C. Y. Chang, H. T. Hsu, E. Y. Chang, C. I. Kuo, Y. Miyamoto. InAs-Channel HEMTs for Ultra- Low-Power LNA Applications, 2008 International Conference on Solid State Devices and Materials, Sept. 2008.
• H. Saito, Y. Miyamoto, K. FUruya. Increment of voltage gain of InP/InGaAs Hot Electron Transistors controlled by insulated gate, International Nano-Optoelectronic Workshop (iNOW 2008), Nano-Optoelectronics Workshop, 2008. i-NOW 2008. International, 355, Aug. 2008.
• Hisashi Saito, Takahiro Hino, Yasuyuki Miyamoto, Kazuhito Furuya. Hot electron transistor controlled by insulated gate with 70nm-wide emitter, IEEE 20th Conference on Indium Phosphide and Related Materials, May 2008.
• Chien-I Kuo, Edward Yi Chang, Chia-Yuan Chang, Heng-Tung Hsu, YASUYUKI MIYAMOTO. Investigation of impact ionization from InXGa1-XAs to InAs channel HEMTs for high speed and low power applications, The 20th Indium Phosphide and Related Material Conf. (IPRM 2008), May 2008.
• Shinnosuke Takahashi, Tsukasa Miura, Hiroaki Yamashita, Yasuyuki Miyamoto, Kazuhito Furuya. DC Characteristics of Heterojunction Bipolar Transistor with Buried SiO2 Wires in Collector, The 34th International Symposium on Compound Semiconductors, Oct. 2007.
• Hiroaki Yamashita, Tsukasa Miura, Shinnosuke Takahashi, YASUYUKI MIYAMOTO, KAZUHITO FURUYA. Fabrication of 200-nm-thick SiO2 wires buried in InP for reduction in collector capacitance in InP/InGaAs DHBT, 7th Topical Workshop on Heterostructure Microelectronics, Aug. 2007.  Official location  
• Chia-Yuan Chang, Edward Yi Chang, Yi-Chung Lien, Yasuyuki Miyamoto, Chien-I Kuo, Sze-Hung Cheng, Li-Hsin Chu. High-PerformanceIn0.52Al0.48As/In0.6Ga0.4AsPower Metamorphic HEMT for Ka-Band Applications,, IEEE International Conference on Semiconductor Electronics, Nov. 2006.
• Y. Miyamoto, R. Nakagawa, I. Kashima, K. Takeuchi, Y. Yamada, T. Fujisaki, M. Ishida, KAZUHITO FURUYA. 25 nm Wide Emitter and Precise Alignment between Gate and Emitter in InP Hot Electron Transistors, The 6th Topical Workshop on Heterostructure Microelectronics (TWHM 2005), Topical Workshop on Heterostructure Microelectronics, pp. TuC-3, Aug. 2005.

Domestic Conference (Reviewed)

• Y. Miyamoto, K. Makiyama. Lateral thickness change of the high-k film on GaN HEMT for uniform electric field, 14th Topical Workshop on Heterostructure Microelectronics, (TWHM 2022), Aug. 2022.

International Conference (Not reviewed / Unknown)

• YASUYUKI MIYAMOTO. The Potential of GaN HEMT on GaN Substrate, Nanotech Malaysia, May 2018.
• Toru Kanazawa, Yasuyuki Miyamoto. Development of Field-Effect Transistor Using 2D Layered Hafnium Disulfide, IWPSD 2017, 2D06, Dec. 2017.
• Y. Miyamoto. Steep slope devices with InGaAs channel for post Si CMOS application, China Semiconductor Technology International Conference (CSTIC) 2016, Mar. 2016.
• Y. Miyamoto, M. Fujimatsu, K. Ohashi, A. Yukimachi, S. Iwata. Steep subthreshold slope in InGaAs MOSFET, SemiconNano2015, Sept. 2015.
• Y. Miyamoto, T. Kanazawa, Y. Yonai, K. Ohsawa, Y. Mishima, M. Fujimatsu, K. Ohashi, S. Nestu, S. Iwata. InGaAs channel for low supply voltage, 2015 International Conference on Solid State Devices and Materials (SSDM), Sept. 2015.
• Y. Miyamoto, T. Kanazawa, Y. Yonai, K. Ohsawa, Y. Mishima, T. Irisawa, M. Oda, T. Tezuka. (Invited) Growth Process for High Performance of InGaAs MOSFETs, 72nd Device Research Conference (DRC), June 2014.
• Y. Miyamoto, T. Kanazawa, Y. Yonai, A. Kato, M. Fujimatsu, M. Kashiwano, K. Ohsawa, K. Ohashi. (Invited) InGaAs MOSFET Source Structures Toward High Speed/low Power Applications, 26th International Conference on InP and Related Materials (IPRM 2014), May 2014.
• Y. Miyamoto, T. Kanazawa, Y. Yonai, A. Kato, K. Ohsawa, M. Oda, T. Irisawa, T. Tezuka. Heavily doped epitaxially grown source in InGaAs MOSFET for high drain current density, 44th IEEE Semiconductor Interface Specialists Conference (SICS 2013), Dec. 2013.
• Y. Miyamoto. InGaAs channel MOSFET for high-speed/low-power application, The 16th International Symposium on the Physics of Semiconductors and Applications (ISPSA), July 2013.
• Y. Miyamoto, H. Saito, T. Kanazawa. Submicron-channel InGaAs MISFET with epitaxially grown source, 10th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Nov. 2010.
• H. Saito, Y. Miyamoto, K. Furuya. Selective undercut etching for ultra narrow mesa structure in vertical InGaAs channel MISFET, Global COE International Symposium, Mar. 2010.
• H. Saito, Y. Miyamoto, K. Furuya. Fabrication of vertical InGaAs channel MISFET with heterostructure launcher and undoped channel, Int. Symposium on Silicon Nano Devices in 2030, Oct. 2009.
• K. Wakabayashi, T. Kanazawa, H. Saito, R. Terao, S. Ikeda, Y. Miyamoto, K. Furuya. InP/In0.53Ga0.47As composite channel n-MOSFETwith heavily dopedregrown source/drain structure, Int. Symposium on Silicon Nano Devices in 2030, Oct. 2009.
• YASUYUKI MIYAMOTO. InGaAs/InP MISFET, Int. Symposium on Silicon Nano Devices in 2030, Oct. 2009.
• YASUYUKI MIYAMOTO, Toru Kanazawa, Hisashi Saito, KAZUHITO FURUYA. InGaAs/InP MISFET with epitaxially grown source, 2009 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices（AWAD）, June 2009.
• N. Kashio, K. Kurishima, Y. Fukai, S. Yamahata, Y. Miyamoto. Emitter layer design for highly reliable and high-speed InP HBTs, 19th International Conference on Indium Phosphide and Related Materials (IPRM’07), pp. PD1, May 2007.
• T. Hino, A. Suwa, T. Hasegawa, H. Saito, M. Oono, Y. Miyamoto, K. Furuya. Fabrication of hot electron transistors controlled by insulated gate, 19th International Conference on Indium Phosphide and Related Materials (IPRM'07), pp. PA-11, May 2007.
• Y. Miyamoto, R. Nakagawa, I. Kashima, A. Suwa, N. Machida, K. Furuya. 25-nm-wide emitter for InP hot electron transistors without base layer, International Topical Workshop "Tera- and Nano-Devices:Physics and Modeling", International Topical Workshop "Tera- and Nano-Devices:Physics and Modeling", pp. III.2, Oct. 2006.
• T. Kai, Y. Fukuyama, Y. Miyamoto, K. Furuya, K. Kurishima, S. Yamahata. Electron Beam Lithography for Non Self-Aligned HBTs with Extremely Narrow Emitter Mesa, 2006 International Microprocesses and Nanotechnology Conference, 2006 International Microprocesses and Nanotechnology Conference, pp. 26A-4-4, Oct. 2006.
• Y. Miyamoto, I. Kashima, A. Suwa, K. Furuya. Increase in current density at 25-nm-wide emitter for InP hot-electron transistors without base layer, 64th Annual Device Research Conference, 64th Annual Device Research Conference, pp. V.A-7, June 2006.
• Y. Miyamoto, M. Ishida, T. Yamamoto, T. Miura, K. Furuya. InP Buried growth of SiO2 wires toward reduction of collector, 13th International Conference on Metalorganic Vapor Phase Epitaxy, 13th International Conference on Metalorganic Vapor Phase Epitaxy, pp. We-A3-1, May 2006.
• N. Machida, Y. Miyamoto, K. Furuya. Minimum emitter charging time for heterojunction bipolar transistors, The 18th Indium Phosphide and Related Materials Conference, The 18th Indium Phosphide and Related Materials Conference, pp. WP16, May 2006.
• K. Furuya, N. Machida, R. Nakagawa, I. Kashima, M. Ishida, Y. Miyamoto. MC simulation and fabrication of ultrafast transistor using ballistic electron in intrinsic semiconductor, Second Joint International Conference on New Phenomena in Mesoscopic Systems and Surfaces and Interfaces of Mesoscopic Devices, Second Joint International Conference on New Phenomena in Mesoscopic Systems and Surfaces and Interfaces of Mesoscopic Devices, pp. P28, Nov. 2005.
• Y. Miyamoto, R. Nakagawa, I. Kashima, M. Ishida, K. Furuya. Low leakage gate current of InP transistors with hot electron extracted by attractive potential around i-InP/metal gate, 2005 International Conference on Solid State Devices and Materials (SSDM 2005), International Conference on Solid State Devices and Materials, pp. I-2-6, Sept. 2005.
• 鹿嶋一生, 古屋一仁, 宮本恭幸, 中川　亮. InP系ホットエレクトロントランジスタにおけるエミッタ接地の飽和特性とゲートリーク電流の低減, 応用物理学会学術講演会, 応用物理学会, 7a-W-11, Sept. 2005.
• Y. Miyamoto, Y. Watanabe, W. Qiu, K. Furaya. Analysis of lateral current spreading in collector of submicron HBT, International Conference on Indium Phosphide and Related, International Conference on Indium Phosphide and Related, pp. WP-15, May 2005.
• Y. Miyamoto, M. Ishida, T. Nonaka, T. Yamamoto, K. Furuya. Tungsten Buried Growth by Using Thin Flow-Liner for Small Collector Capacitance in InP HBT, International Conference on Indium Phosphide and Related, International Conference on Indium Phosphide and Related, pp. TuA-1-4, May 2005.

Domestic Conference (Not reviewed / Unknown)

• Takahiro Arai, Tomoya Aota, isao makabe, 中田健, Takahiro Gotow, YASUYUKI MIYAMOTO. N極性GaN HEMTのTMAHによる素子分離, 第69回応用物理学会春季学術講演会, Mar. 2022.
• Takahiro Gotow, Tatsushi Suka, YASUYUKI MIYAMOTO. N極性およびGa極性GaN MIS構造の界面特性の比較検討, 第82回応用物理学会秋季学術講演会, Sept. 2021.
• YASUYUKI MIYAMOTO, Takahiro Gotow. 界面電荷量によるGaN HEMTの耐圧制御の提案, 電子デバイス研究会, Mar. 2021.
• Tomoya Aota, Akihiro Hayasaka, isao makabe, Shigeki Yoshida, Takahiro Gotow, YASUYUKI MIYAMOTO. N極性GaN HEMT構造での無電極PECエッチング, 第81回 応用物理学会秋季学術講演会, Sept. 2020.
• Masahiro Mori, Akihiro Hayasaka, 眞壁 勇夫, 吉田 成輝, Takahiro Gotow, YASUYUKI MIYAMOTO. N極性GaN HEMT構造におけるコンタクト抵抗の低減, 第67回 応用物理学会 春季学術講演会, 12p-B401-12, Mar. 2020.
• Akihiro Hayasaka, Ryousuke Aonuma, Koushi Hotta, Nanae Kanai, 眞壁 勇夫, 吉田 成輝, YASUYUKI MIYAMOTO. N極性GaN HEMT作製プロセスにおけるプラズマダメージの低減, 第80回 応用物理学会 秋季学術講演会, 18p-N302-11, Sept. 2019.
• Moataz Eissa, Takuya Mitarai, Tomohiro Amemiya, Nobuhiko Nishiyama, Yasuyuki Miyamoto. Fabrication of Si Photonics Waveguides by Thick Resist-Mask Electron Beam Lithography Proximity Effect Correction, 第80回応用物理学会秋季学術講演会, Sept. 2019.
• Akihiro Hayasaka, Ryousuke Aonuma, Koushi Hotta, 眞壁 勇夫, 吉田 成輝, YASUYUKI MIYAMOTO. Al2O3ゲート絶縁膜を持つN極性GaN HEMT, 第66回応用物理学会春季学術講演会, 9p-M121-13, Mar. 2019.
• Wenlun Zhang, Toru Kanazawa, Minoru Kitamura, YASUYUKI MIYAMOTO. UV-O3表面酸化によるHfS2 MOSFETの性能改善, 第66回応用物理学会春季学術講演会, 11p-W521-4, Mar. 2019.
• Tomohiro Amemiya, Tomoya Yoshida, Yuki Atsumi, nobuhiko nishiyama, YASUYUKI MIYAMOTO, Yoichi Sakakibara, SHIGEHISA ARAI. Siフォトニクスによる光渦MUX/DEMUXモジュール, 電子情報通信学会 2018年総合大会, Mar. 2019.
• Minoru Kitamura, Toru Kanazawa, YASUYUKI MIYAMOTO. HSQを用いたInGaAsナノシート構造作製法評価, 第66回応用物理学会春季学術講演会, 11a-M121-11, Mar. 2019.
• Naoya Nogami, Koichi Fukuda, YASUYUKI MIYAMOTO. 量子効果の影響を考慮したGaAsSb/InGaAs Double-Gate Tunnel FETの検討, 第66回応用物理学会春季学術講演会, 9p-S221-4, Mar. 2019.
• Tomohiro Amemiya, 吉田 知也, 渥美 祐樹, Nobuhiko Nishiyama, YASUYUKI MIYAMOTO, 榊原 陽一, SHIGEHISA ARAI. Siフォトニクスによる光渦MUX/DEMUXモジュール, 電子情報通信学会技術研究報告, 118(252), 75-80, Oct. 2018.
• Shinjiro Iwata, Kazumi Ohashi, Netsu Seikou, Koichi Fukuda, YASUYUKI MIYAMOTO. GaAsSb/InGaAsヘテロ接合を用いたダブルゲートトンネルFETにおける界面準位の導入による性能の劣化, 第76回応用物理学会秋季学術講演会, 16a-1C-6, Sept. 2018.
• 吉田匡廣, 比嘉康貴, Nobuhiko Nishiyama, YASUYUKI MIYAMOTO, 加木信行. 測距用14xx-nm Eye-safe波長帯高出力エピタキシャルスタックパルスレーザ, 電子情報通信学会エレクトロニクスソサエティ大会, C-4-5, Sept. 2018.
• Wenlun Zhang, Netsu Seikou, Toru Kanazawa, Tomohiro Amemiya, YASUYUKI MIYAMOTO. 埋め込みNiバックゲートを用いたp-MoS2/HfS2トンネルFET, 第79回応用物理学会秋季学術講演会, 19a-212B-5, Sept. 2018.
• Tomohiro Amemiya, 吉田 知也, Yuki Atsumi, Nobuhiko Nishiyama, YASUYUKI MIYAMOTO, 榊原 陽一, SHIGEHISA ARAI. Si湾曲カプラを用いた光渦MUX/DEMUXモジュール, 第79回応用物理学会秋季学術講演会, 18p-212A-10, Sept. 2018.
• Koushi Hotta, Yumiko Tomizuka, Kosuke Itagaki, 眞壁 勇夫, 吉田 成輝, YASUYUKI MIYAMOTO. N極性GaN HEMT構造のコンタクト抵抗の熱処理温度依存性, 第79回応用物理学会秋季学術講演会, 20p-331-10, Sept. 2018.
• Ryousuke Aonuma, Nobukazu Kise, YASUYUKI MIYAMOTO. Al2O3/ZrO2ゲート絶縁膜を使用したことによるGaAsSb/InGaAsダブルゲートトンネルFETの性能改善, 第79回応用物理学会秋季学術講演会, 21p-331-7, Sept. 2018.
• Nobukazu Kise, Ryousuke Aonuma, YASUYUKI MIYAMOTO. GaAsSb/InGaAsダブルゲートトンネルFETにおけるゲート金属形成プロセスの影響, 第65回応用物理学会春季学術講演会, 18p-C302-12, Mar. 2018.
• Syougo Kunisada, Koichi Fukuda, YASUYUKI MIYAMOTO. GaAsSb/InGaAsダブルゲートTunnel FETにおける量子効果の検討‐正孔バンドの取り扱い, 第65回応用物理学会春季学術講演会, 18a-G203-7, Mar. 2018.
• Toru Kanazawa, Kazuto Ohsawa, Tomohiro Amemiya, Nobukazu Kise, Ryousuke Aonuma, YASUYUKI MIYAMOTO. InGaAsナノシートトランジスタの作製, 第65回応用物理学会春季学術講演会, 18a-G203-3, Mar. 2018.
• Nobukazu Kise, Shinjiro Iwata, Ryousuke Aonuma, YASUYUKI MIYAMOTO. [8a-S22-1] 68mV/decのSSをもつGaAsSb/InGaAsダブルゲートトンネルFET, 第78回応用物理学会秋季学術講演会, Sept. 2017.
• Kazuto Ohsawa, Toru Kanazawa, Nobukazu Kise, Tomohiro Amemiya, YASUYUKI MIYAMOTO. InGaAsナノシートチャネルを持つマルチゲートMOSFETに向けた作製プロセス開発, 第78回応用物理学会秋季学術講演会, No. 8a-S22-2, Sept. 2017.
• Netsu Seikou, Toru Kanazawa, Tomohiro Amemiya, YASUYUKI MIYAMOTO. HfS2/MoS2 ヘテロジャンクションの温度依存電流特性, 第78回応用物理学会秋季学術講演会, No. 7p-C11-16, Sept. 2017.
• Syougo Kunisada, Koichi Fukuda, YASUYUKI MIYAMOTO. [8a-C18-3] InGaAs/GaAsSbダブルゲートTunnel FETにおける量子効果の影響, 第78回応用物理学会秋季学術講演会, Sept. 2017.
• YASUYUKI MIYAMOTO. ヘテロ構造電子デバイスとMOVPE/MBE (チュートリアル講演), 第9回 ナノ構造・エピタキシャル成長講演会, T-Fr-1, July 2017.
• Shinjiro Iwata, Nobukazu Kise, Ryousuke Aonuma, YASUYUKI MIYAMOTO. [16p-412-5] GaAsSb/InGaAsヘテロ接合を用いたダブルゲートトンネルFETにおける不純物濃度調整によるオン電流の向上, 第64回応用物理学会春季学術講演会, Mar. 2017.
• Toru Kanazawa, Tomohiro Amemiya, Netsu Seikou, Vikrant Upadhyaya, Koichi Fukuda, YASUYUKI MIYAMOTO. HfS2系トンネルトランジスタのデバイスシミュレーション, 第64回応用物理学会春季学術講演会, 16a-F203-3, Mar. 2017.
• Kazuto Ohsawa, Shinji Noguchi, Netsu Seikou, Nobukazu Kise, YASUYUKI MIYAMOTO. [16p-413-11] HfO2/Al2O3/InGaAsゲート構造をもつMOSFETの移動度のH2アニール後における成膜温度およびAl2O3膜厚依存性, 第64回応用物理学会春季学術講演会, Mar. 2017.
• Ryousuke Aonuma, Shinjiro Iwata, Nobukazu Kise, YASUYUKI MIYAMOTO. 68mV/decのSSを持つGaAsSb/InGaAs縦型ダブルゲートトンネルFET, 電気学会電子デバイス研究会, EDD-17-051, Mar. 2017.
• Netsu Seikou, Toru Kanazawa, Vikrant Upadhyaya, ウワンノー ティーラユット, Tomohiro Amemiya, 長汐 晃輔, YASUYUKI MIYAMOTO. Type II 型 HfS2/MoS2ヘテロジャンクションを有するTFET, 第64回応用物理学会春季学術講演会, 16a-F203-4, Mar. 2017.
• Kazuto Ohsawa, Shinji Noguchi, Netsu Seikou, Nobukazu Kise, YASUYUKI MIYAMOTO. HfO2/Al2O3/InGaAsゲート構造における移動度への成膜温度およびH2アニールの影響, 電子情報通信学会電子デバイス研究会, 信学技報, vol. 116, no. 431, pp. 35-40, Jan. 2017.
• Tomohiro Amemiya, Satoshi Yamasaki, Toru Kanazawa, Atsushi Ishikawa, Nobuhiko Nishiyama, YASUYUKI MIYAMOTO, Takuo Tanaka, SHIGEHISA ARAI. 光回路とプラズモニックメタマテリアル, 第37回レーザー学会年次大会, No. 07pII.7, Jan. 2017.
• Toru Kanazawa, Vikrant Upadhyaya, Tomohiro Amemiya, Atsushi Ishikawa, 鶴田 健二, Takuo Tanaka, YASUYUKI MIYAMOTO. HfO2パッシベーションによるHfS2 FETの特性改善, 第77回応用物理学会秋季学術講演会, No. 16a-A32-3, Sept. 2016.
• Kazuto Ohsawa, Nobukazu Kise, YASUYUKI MIYAMOTO. 15p-B9-10 HfO2/Al2O3/InGaAsゲート構造における移動度の成膜温度およびAl2O3膜厚依存性, 第77回応用物理学会秋季学術講演会, Sept. 2016.
• Vikrant Upadhyaya, Toru Kanazawa, Yasuyuki Miyamoto. Evaluation of electrical properties of HfS₂ thin flakes obtained by mechanical exfoliation, 電子情報通信学会電子デバイス研究会, 信学技報, vol. 116, no. 48, pp. 47-50, May 2016.
• Wenbo Lin, Shinjiro Iwata, Koichi Fukuda, YASUYUKI MIYAMOTO. Contribution to Off-Current of Source-Drain Direct Tunneling in Short-Channel TFET, The 63rd JSAP Spring Meeting 2016, Mar. 2016.  Official location  
• Haruki Kinoshita, Nobukazu Kise, Netsu Seikou, Toru Kanazawa, YASUYUKI MIYAMOTO. 再成長S/Dを有するInGaAsマルチゲートMOSFETのLch=16nm動作, 第63回応用物理学会春季学術講演会, 22p-W541-5, Mar. 2016.
• Upadhyaya Vikrant, kanazawa Toru, Miyamoto Yasuyuki. Measures for mitigating environmental degradation of Two Dimensional Hafnium Disulfide Field Effect Transistor, 第63回応用物理学会春季学術講演会, 21p-H103-2, Mar. 2016.
• Haruki Kinoshita, Nobukazu Kise, Netsu Seikou, Toru Kanazawa, YASUYUKI MIYAMOTO. [22p-W541-5] 再成長S/Dを有するInGaAsマルチゲートMOSFETのLch=16nm動作, 第63回応用物理学会春季学術講演会, Mar. 2016.
• Haruki Kinoshita, Toru Kanazawa, Netsu Seikou, Yuichi Mishima, YASUYUKI MIYAMOTO. 再成長ソース/ドレインを有するInGaAsマルチゲートMOSFET作製プロセス, 第76回応用物理学会秋季学術講演会, 16a-1C-9, Sept. 2015.
• Atsushi Yukimachi, YASUYUKI MIYAMOTO. 超格子FET のためのAlAs/InGaAsダブルバリアp-i-n 接合ダイオード, 第76回応用物理学会秋季学術講演会, 16a-4C-3, Sept. 2015.
• Tomohiro Amemiya, Atsushi Ishikawa, Toru Kanazawa, Nobuhiko Nishiyama, YASUYUKI MIYAMOTO, Takuo Tanaka, SHIGEHISA ARAI. 光通信素子における透磁率制御の可能性, 第136回微小光学研究会, May 2015.
• Atsushi Yukimachi, Masashi Kashiwano, YASUYUKI MIYAMOTO. 超格子FETに向けたダブルバリアp-i-n接合ダイオード, 第62回応用物理学会春季学術講演会, Mar. 2015.
• Netsu Seikou, Toru Kanazawa, YASUYUKI MIYAMOTO. HfO2/Al2O3/In0.53Ga0.47As界 面に対する窒素プラズマクリーニング後の水素アニール効果に関する研究, 第62回応用物理学会春季学術講演会, Mar. 2015.
• Haruki Kinoshita, Toru Kanazawa, Netsu Seikou, Yuichi Mishima, YASUYUKI MIYAMOTO. 再成長ソース/ドレインを有するInGaAsマルチゲートMOSFET作製プロセスに関する研究, 第62回応用物理学会春季学術講演会, Mar. 2015.
• Kazuto Ohsawa, Yuichi Mishima, YASUYUKI MIYAMOTO. InGaAs-MOSFETのチャネル長微細化に関する研究, 第62回応用物理学会春季学術講演会, Mar. 2015.
• YASUYUKI MIYAMOTO, Atsushi Yukimachi. 超格子ソースによるスティープスロープFETの可能性, 電子情報通信学会 総合大会, Mar. 2015.
• Shinjiro Iwata, Kazumi Ohashi, YASUYUKI MIYAMOTO. GaAsSb/InGaAsヘテロ接合を用いたダブルゲートトンネルFETにおけるI-V特性の不純物濃度依存性, 電子情報通信学会 総合大会, Mar. 2015.
• Toru Kanazawa, Tomohiro Amemiya, Atsushi Ishikawa, Kenji Tsuruta, Takuo Tanaka, YASUYUKI MIYAMOTO. 薄膜HfS2 FET, 第62回応用物理学会春季学術講演会, No. 14p-D7-6, Mar. 2015.
• Atsushi Ishikawa, Toru Kanazawa, Tomohiro Amemiya, Kenji Tsuruta, Takuo Tanaka, YASUYUKI MIYAMOTO. 機械的剥離法を用いたHfS2原子薄膜の作製と基礎物性の評価, 第62回応用物理学会春季学術講演会, No. 11a-P6-27, Mar. 2015.
• Kazumi Ohashi, Motohiko Fujimatsu, YASUYUKI MIYAMOTO. GaAsSb/InGaAsヘテロ接合を用いたダブルゲートトンネルFETにおける SSとON電流のボディ幅依存性, 第75回応用物理学会秋季学術講演会, Sept. 2014.
• Tomohiro Amemiya, Toru Kanazawa, Atsushi Ishikawa, JoonHyun Kang, Zhichen Gu, Nobuhiko Nishiyama, YASUYUKI MIYAMOTO, Takuo Tanaka, SHIGEHISA ARAI. ［依頼講演］透磁率制御メタマテリアルを装荷した光変調器, 電気情報通信学会 2014年ソサイエティ大会, Sept. 2014.
• YASUYUKI MIYAMOTO. 低消費電力と高速動作を両立させるInP系電子デバイス, 電子情報通信学会 エレクトロニクスソサエティ大会, エレクトロニクスソサエティ受賞記念講演, Sept. 2014.
• Ryota Yamanaka, Toru Kanazawa, 柳生栄治, YASUYUKI MIYAMOTO. デジタルエッチングを用いたGaN HEMTのノーマリーオフ化, 第75回応用物理学会秋季学術講演会, Sept. 2014.
• YASUYUKI MIYAMOTO, Toru Kanazawa, Yosiharu Yonai, atsushi kato, Motohiko Fujimatsu, Masashi Kashiwano, Kazuto Ohsawa, Kazumi Ohashi. 低電圧/高速動作にむけたInGaAs MOSFETソース構造, 電子情報通信学会 電子デバイス研究会, IEICE Technical Report, Aug. 2014.
• Kazumi Ohashi, Motohiko Fujimatsu, YASUYUKI MIYAMOTO. GaAsSb/InGaAsヘテロ接合を用いたDouble-Gate Tunnel FETの理論特性とその実験的検証, 電子情報通信学会 電子デバイス研究会, IEICE Technical Report, Aug. 2014.
• 入澤寿史, 小田穣, 池田圭司, 守山佳彦, 三枝栄子, JevaswanWipakorn, 前田辰朗, 市川麿, 長田剛規, YASUYUKI MIYAMOTO, 秦雅彦, 手塚勉. 高移動度(111)B面をチャネルに有する三角形状InGaAs-OI nMOSFET, 第61回春季応用物理学会学術講演会, Mar. 2014.
• 入澤寿史, 小田穣, 池田圭司, 守山佳彦, 三枝栄子, JevaswanWipakorn, 前田辰朗, 市川麿, 長田剛規, YASUYUKI MIYAMOTO, 秦雅彦, 手塚勉. MOVPE再成長により形成した(111)B面を有する高移動度三角形状InGaAs-OI nMOSFET, 電気学会電子デバイス研究会, Mar. 2014.
• 大石敏之, Yuutarou Yamaguchi, 大塚浩志, 山中宏治, 野上洋一, 福本宏, YASUYUKI MIYAMOTO. GaNショットキーバリアダイオードの温度依存性モデル, 第61回春季応用物理学会学術講演会, Mar. 2014.
• Yuutarou Yamaguchi, 大石敏之, 大塚浩志, 山中宏治, TeoKoonHoo, YASUYUKI MIYAMOTO. GaN HEMTの過渡応答バイアス依存性によるトラップ解析, 第61回春季応用物理学会学術講演会, Mar. 2014.
• Yuichi Mishima, Toru Kanazawa, Haruki Kinoshita, Eiji Uehara, YASUYUKI MIYAMOTO. 再成長ソース/ドレインを有するInGaAsチャネルトライゲートMOSFET, 第61回春季応用 物理学会学術講演会, Mar. 2014.
• 入澤寿史, 小田穣, 池田圭司, 守山佳彦, 三枝栄子, JevaswanWipakorn, 前田辰朗, 市川麿, 長田剛規, YASUYUKI MIYAMOTO, 秦雅彦, 手塚勉. MOVPE再成長により形成した(111)B面を有する高移動度三角形状InGaAs-OI nMOSFET, 電子情報通信学会 シリコン材料・デバイス研究会, Jan. 2014.
• Toru Kanazawa, Yuichi Mishima, Haruki Kinoshita, Eiji Uehara, YASUYUKI MIYAMOTO. MOVPE再成長ソース/ドレインを有するInGaAsトライゲートMOSFET, 電子情報通信学 会 電子デバイス研究会, IEICE technical report, Jan. 2014.
• Tomohiro Amemiya, Toru Kanazawa, Atsushi Ishikawa, JoonHyun Kang, Nobuhiko Nishiyama, YASUYUKI MIYAMOTO, Takuo Tanaka, SHIGEHISA ARAI. メタマテリアルを用いたInP系プラットフォームにおける透磁率制御, 電子情報通信学会 光エレクトロニクス研究会（OPE）, IEICE Technical Report, Vol. 113, No. 370, pp. 45-50, Dec. 2013.
• 山口 裕太郎, 林 一夫, 大石 敏之, 大塚 浩志, 山中 宏治, YASUYUKI MIYAMOTO. C-10-1 ソースフィールドプレートGaN HEMTのドレインソース間容量とドレイン抵抗のトレードオフの解析(C-10.電子デバイス,一般セッション), 電子情報通信学会ソサイエティ大会講演論文集, 一般社団法人電子情報通信学会, Vol. 2013, No. 2, pp. 53, Sept. 2013.
• YASUYUKI MIYAMOTO, Toru Kanazawa. InGaAs MOSFETの現状と将来展望, 電気学会 電子・情報・システム部門大会, Sept. 2013.
• Masashi Kashiwano, Atsushi Yukimachi, YASUYUKI MIYAMOTO. 急峻なSS特性の為のInGaAs/InP超格子FETにおけるキャリア濃度依存性, 第74回秋季応用物理学会学術講演会, Sept. 2013.
• Kazuto Ohsawa, atsushi kato, Takeru Sagai, Toru Kanazawa, Eiji Uehara, YASUYUKI MIYAMOTO. 高電流密度化に向けたInPソースを有するIII-V-OI InGaAs MOSFETのチャネル厚依存性, 第74回秋季応用物理学会学術講演会, Sept. 2013.
• YASUYUKI MIYAMOTO. 超高速トランジスタ技術の現状と展望, 2013年電子情報通信学会総合大会, Mar. 2013.
• YASUYUKI MIYAMOTO. 東工大の微細加工プラットフォームにおける支援事例, 日本化学会第93春季年会, Mar. 2013.
• atsushi kato, Yosiharu Yonai, Toru Kanazawa, YASUYUKI MIYAMOTO. Si 基板上 InGaAs-MOSFET の微細化に関する研究, 第 60 回応用物理学会春季学術講演会, Mar. 2013.
• Tomohiro Amemiya, Toru Kanazawa, Atsushi Ishikawa, Seiji Miyouga, Eijun Murai, Takahiko Shindou, JoonHyun Kang, Nobuhiko Nishiyama, YASUYUKI MIYAMOTO, Takuo Tanaka, SHIGEHISA ARAI. 微細金属構造をもつ導波路型光デバイスにおける相互作用距離の解析, 第60回応用物理学関係連合講演会, 第60回応用物理学関係連合講演会, 29p-B3-14, Mar. 2013.
• YASUYUKI MIYAMOTO, Motohiko Fujimatsu. GaAsSb/InGaAs 縦型トンネル FET, 電気学会電子デバイス研究会, Mar. 2013.
• Takeru Sagai, Eiji Uehara, Kazuto Ohsawa, YASUYUKI MIYAMOTO. n-InP ソースを持つT ゲート構造 InGaAs-MOSFET の高周波特性, 2013年電子情報通信学会総合大会, Mar. 2013.
• YASUYUKI MIYAMOTO. 微細加工ナノプラットフォームコンソーシアムによる設備共用の取り組み, 電子情報通信学会シリコンフォトニクスファウンドリユーザー及びポテンシャルユーザーズフォーラム, Jan. 2013.
• YASUYUKI MIYAMOTO, Toru Kanazawa. MOSFET低電圧化の為のInGaAs チャネル, 応用物理学会北陸・信越支部学術講演会, Nov. 2012.
• Tomohiro Amemiya, Toru Kanazawa, Atsushi Ishikawa, Seiji Miyouga, Eijun Murai, Takahiko Shindou, JoonHyun Kang, Nobuhiko Nishiyama, YASUYUKI MIYAMOTO, Takuo Tanaka, SHIGEHISA ARAI. ---, 第73回秋季応用物理学会学術講演会, Vol. 愛媛, No. 13p-C5-3, Sept. 2012.
• Motohiko Fujimatsu, YASUYUKI MIYAMOTO. GaAsSb/InGaAs ヘテロ接合を用いた縦型トンネル FET における サブスレッショルドスロープの改善, 第 73 回応用物理学会学術講演会, Sept. 2012.
• atsushi kato, Yosiharu Yonai, Toru Kanazawa, YASUYUKI MIYAMOTO. Si 基板上 InGaAs-MOSFET の微細化に関する研究, 第73 回応用物理学会学術講演会, Sept. 2012.
• Masashi Kashiwano, Jun Hirai, Shunsuke Ikeda, Motohiko Fujimatsu, YASUYUKI MIYAMOTO. 半導体ドレイン層及び狭チャネルメサ幅による縦型 InGaAs チャネル MISFET の高電圧利得化, 第 73 回応用物理学会学術講演会, Sept. 2012.
• Takeru Sagai, Yosiharu Yonai, YASUYUKI MIYAMOTO. InGaAs チャネル MOSFET の EOT 削減による 伝達コンダクタンス向上, 第 73 回応用物理学会学術講演会, Sept. 2012.
• Keishi Tanaka, YASUYUKI MIYAMOTO. 55 nm 幅エミッタInP HBT および電流密度とエミッタ幅の関係, 第 73 回応用物理学会学術講演会, Sept. 2012.
• 大石敏之, 林一夫, 佐々木肇, Yuutarou Yamaguchi, 大塚浩志, 山中宏治, 中山正敏, YASUYUKI MIYAMOTO. トランジスタ動作時における GaN HEMT ゲートリークのデバイスシミュレーションによる解析, 電子情報通信学会2012年ソサエティ大会, Sept. 2012.
• 山口 裕太郎, 林 一夫, 大石 敏之, 大塚 浩志, 小山 英寿, 加茂 宣卓, 山中 宏治, 中山 正敏, YASUYUKI MIYAMOTO. C-10-5 GaN HEMTの電界とゲートドレイン間容量のトレードオフとPAEへの影響についてのシミュレーション解析(C-10. 電子デバイス,一般セッション), 電子情報通信学会ソサイエティ大会講演論文集, 一般社団法人電子情報通信学会, Vol. 2012, No. 2, pp. 62, Aug. 2012.
• Masashi Kashiwano, Jun Hirai, Shunsuke Ikeda, Motohiko Fujimatsu, YASUYUKI MIYAMOTO. 半導体ドレイン層及び狭チャネルメサ幅による縦型InGaAsチャネルMISFETの高電圧利得化, 電子情報通信学会技術研究報告, May 2012.
• YASUYUKI MIYAMOTO, Yosiharu Yonai, Toru Kanazawa. エピタキシャル成長ソースによるInGaAsMOSFETの高電流密度化, 電気学会電子デバイス研究会, Mar. 2012.
• YASUYUKI MIYAMOTO, Yosiharu Yonai, Toru Kanazawa. エヒ?タキシャル成長ソースによる InGaAs MOSFET の高電流密度化, 電気学会電子デバイス研究会, Mar. 2012.
• Yosiharu Yonai, Toru Kanazawa, Shunsuke Ikeda, YASUYUKI MIYAMOTO. InPエッチング異方性による微細InGaAsチャネルMOSFET, 応用物理学会 2012年度春季大会, Mar. 2012.
• Yuutarou Yamaguchi, 大石敏之, 大塚浩志, 山中宏治, 南條拓真, 中山正敏, 平野嘉仁, YASUYUKI MIYAMOTO. デバイスシミュレーションによるGaN HEMTのゲートリークの解析, 電子情報通信学会2011年総合大会, Mar. 2012.
• Masashi Kashiwano, Jun Hirai, Shunsuke Ikeda, Motohiko Fujimatsu, YASUYUKI MIYAMOTO. GaN HEMT のソース・ドレイン間容量のデバイスシミュレーションによる解析, 電子情報通信学会2011年総合大会, Mar. 2012.
• YASUYUKI MIYAMOTO, Masayuki Yamada, Ken Uchida. InGaAs MOSFETにおけるソース充電時間の検討, 電子情報通信学会技術研究報告, Jan. 2012.
• YASUYUKI MIYAMOTO, Yosiharu Yonai, Toru Kanazawa. InGaAs MOSFETの高電流密度化, 電子情報通信学会技術研究報告, Jan. 2012.
• YASUYUKI MIYAMOTO, Yosiharu Yonai, Toru Kanazawa. InGaAs MOSFETの高電流密度化, 電子情報通信学会 電子デバイス研究会（ED）, Dec. 2011.
• Motohiko Fujimatsu, Hisashi Saito, YASUYUKI MIYAMOTO. GaAsSb/InGaAsヘテロ接合を用いた縦型トンネルFETの作製・評価, 電子情報通信学会2011年ソサイエティ大会, Sept. 2011.
• YASUYUKI MIYAMOTO, Toru Kanazawa. InP系化合物半導体を用いたMOSFETの技術動向, 電気学会 電子・情報・システム部門大会, Sept. 2011.
• Shunsuke Ikeda, Toru Kanazawa, YASUYUKI MIYAMOTO. 電子ランチャを持つInGaAs MOSFETにおけるヘテロ障壁高さ依存性, 電子情報通信学会2011年ソサイエティ大会, Sept. 2011.
• Atsushi Kato, Toru Kanazawa, YASUYUKI MIYAMOTO. ソース裏面電極によるInP/InGaAsコンポジットチャネルMOSFETのアクセス抵抗低減, 電子情報通信学会2011年ソサイエティ大会, Sept. 2011.
• 大石 敏之, 大塚 浩志, 山中 宏治, 中山 正敏, 平野 嘉仁, YASUYUKI MIYAMOTO. C-10-7 緑色光照射時の等価回路パラメータ測定によるGaN HEMTのトラップ解析(C-10.電子デバイス,一般セッション), 電子情報通信学会ソサイエティ大会講演論文集, 一般社団法人電子情報通信学会, Vol. 2011, No. 2, pp. 61, Aug. 2011.
• Yuutarou Yamaguchi, Takeru Sagai, YASUYUKI MIYAMOTO. 基板転写プロセスを用いたSi基板上InP/InGaAs SHBTの作製, 第58回応用物理学会関係連合講演会, Apr. 2011.
• Naoaki Takebe, YASUYUKI MIYAMOTO. InP/InGaAs DHBT におけるSiO2細線埋め込みによるベースコレクタ間容量の削減, 第58回応用物理学会関係連合講演会, Apr. 2011.
• Yutaka Matsumoto, Hisashi Saito, YASUYUKI MIYAMOTO. 縦型InGaAs MIS-FETのソース寄生容量の削減, 電気学会電子デバイス研究会, Mar. 2011.
• Motohiko Fujimatsu, Hisashi Saito, Tomoki Kususaki, Yutaka Matsumoto, Jun Hirai, YASUYUKI MIYAMOTO. GaAsSb/InGaAsヘテロ接合を用いた縦型トンネルFETに関する研究, 第58回応用物理学会関係連合講演会, Mar. 2011.
• Toru Kanazawa, Ryousuke Terao, Yuutarou Yamaguchi, Shunsuke Ikeda, Yosiharu Yonai, atsushi kato, YASUYUKI MIYAMOTO. 裏面電極を有するⅢ－Ⅴ族量子井戸型チャネルMOSFET, 電子情報通信学会電子デバイス研究会, Jan. 2011.
• Ryousuke Terao, Toru Kanazawa, Shunsuke Ikeda, Yosiharu Yonai, atsushi kato, YASUYUKI MIYAMOTO. Submicron InP/InGaAs channel n-MOSFET with regrown InGaAs and Al2O3 gate dielectric, 第71回応用物理学会学術講演会, Sept. 2010.
• Toru Kanazawa, Ryousuke Terao, Yuutarou Yamaguchi, Shunsuke Ikeda, Yosiharu Yonai, atsushi kato, YASUYUKI MIYAMOTO. InP/InGaAs MOSFET with back-gate electrode bonded on Si substrate, 第71回応用物理学会学術講演会, Sept. 2010.
• YASUYUKI MIYAMOTO. CI-2-2 HMET,HBTによるTHz波源(CI-2.テラヘルツ波源デバイスの現状と展望,依頼シンポジウム,ソサイエティ企画), 電子情報通信学会ソサイエティ大会講演論文集, 一般社団法人電子情報通信学会, Vol. 2010, No. 2, pp. "SS-17"-"SS-18", Aug. 2010.
• Ryousuke Terao, Toru Kanazawa, Hisashi Saito, kazuya wakabayashi, Shunsuke Ikeda, YASUYUKI MIYAMOTO, KAZUHITO FURUYA. Al2O3ゲート絶縁膜を用いたInP/InGaAsチャネル n-MOSFETの電気特, 第57回応用物理学関係連合研究会, Mar. 2010.
• Toru Kanazawa, kazuya wakabayashi, Hisashi Saito, Ryousuke Terao, Tomonori Tajima, Shunsuke Ikeda, YASUYUKI MIYAMOTO, KAZUHITO FURUYA. III-V族サブミクロンチャネルを有する高移動度MOSFET, 電気学会電子デバイス研究会, Mar. 2010.
• Takashi Kobayashi, Hiroyuki Suzuki, Naoaki Takebe, YASUYUKI MIYAMOTO, KAZUHITO FURUYA. SiO2細線埋め込みInP/InGaAs DHBTの作製, 第57回応用物理学関係連合研究会, Mar. 2010.
• Hisashi Saito, Tomoki Kususaki, Yutaka Matsumoto, YASUYUKI MIYAMOTO, KAZUHITO FURUYA. 縦型InGaAs チャネルMISFET の極微細メサに向けた選択的ウェットエッチング, 第57回応用物理学関係連合研究会, Mar. 2010.
• Yuji Isogai, Takashi Kobayashi, Yuutarou Yamaguchi, YASUYUKI MIYAMOTO, KAZUHITO FURUYA. Si基板上へ転写したInP系HBTの動作, 第57回応用物理学関係連合研究会, Mar. 2010.
• kazuya wakabayashi, Toru Kanazawa, Hisashi Saito, Ryousuke Terao, Shunsuke Ikeda, YASUYUKI MIYAMOTO, KAZUHITO FURUYA. 再成長ソースを有するサブミクロンInP/InGaAs nMOSFETの電流電圧特性, 第57回応用物理学関係連合研究会, Mar. 2010.
• Toru Kanazawa, kazuya wakabayashi, Hisashi Saito, Ryousuke Terao, Tomonori Tajima, Shunsuke Ikeda, YASUYUKI MIYAMOTO, KAZUHITO FURUYA. InP/InGaAs composite channel MOSFET with Al2O3 gate dielectric, IEICE Technical Report, Electron Devices, IEICE Technical Report, Electron Devices, Vol. 109, No. 360, pp. 39-42, Jan. 2010.
• YASUYUKI MIYAMOTO. テラヘルツ帯におけるトランジスタ, 応用物理学会応用電子物性分科会, Jan. 2010.
• Masayuki Yamada, Takafumi Uesawa, YASUYUKI MIYAMOTO, KAZUHITO FURUYA. HBTにおける高電流密度動作時エミッタ充電時間の電流反比例特性からの逸脱, 電子情報通信学会電子デバイス研究会, 電子情報通信学会技術研究報告 電子デバイス, Jan. 2010.
• Naoaki Takebe, Hiroaki Yamashita, Shinnosuke Takahashi, YASUYUKI MIYAMOTO, KAZUHITO FURUYA. SiO2細線埋込InP系HBTにおけるCBr4を使ったin-situエッチング, 第70回応用物理学会学術講演会, Sept. 2009.
• kazuya wakabayashi, Toru Kanazawa, Hisashi Saito, Tomonori Tajima, Ryousuke Terao, YASUYUKI MIYAMOTO, KAZUHITO FURUYA. 「再成長ソースを有するアンドープチャネルInP/InGaAs MOSFETの電流特性, 第70回応用物理学会学術講演会, Sept. 2009.
• Hisashi Saito, Tomoki Kususaki, Yutaka Matsumoto, YASUYUKI MIYAMOTO, KAZUHITO FURUYA. ヘテロランチャと真性チャネルを有する縦型InGaAs-MISFET の高駆動能力動作, 第70回応用物理学会学術講演会, Sept. 2009.
• Tomoki Kususaki, Hisashi Saito, Yutaka Matsumoto, YASUYUKI MIYAMOTO, KAZUHITO FURUYA. 縦型InGaAs-MISFETの試作, 第70回応用物理学会学術講演会, Sept. 2009.
• Kazuya Wakabayashi, Toru Kanazawa, Hisashi Saito, Tomonori Tajima, Ryosuke Terao, YASUYUKI MIYAMOTO, KAZUHITO FURUYA. I-V characteristics of undoped channel InP/InGaAs MOSFET with regrown source region, The 70th Autumn Meeting, 2008; The Japan Society of Applied Physics, pp. 1299, Sept. 2009.
• Masayuki Yamada, Takafumi Uesawa, YASUYUKI MIYAMOTO, KAZUHITO FURUYA. HBTにおける超高速動作時エミッタ充電時間の理論的解析, 第70回応用物理学会学術講演会, Sept. 2009.
• Toru Kanazawa, Hisashi Saito, kazuya wakabayashi, Tomonori Tajima, YASUYUKI MIYAMOTO, KAZUHITO FURUYA. High mobility III-V MOSFET with n⁺-source regrown by MOSFET, 電気学会 電子・情報・システム部門大会, Sept. 2009.
• Naoaki Takebe, Hiroaki Yamashita, Shinnosuke Takahashi, Hisashi Saito, Takashi Kobayashi, YASUYUKI MIYAMOTO, KAZUHITO FURUYA. SiO2細線埋込InP系HBTにおけるCBr4を使ったIn-situエッチング, 電子情報通信学会電子デバイス研究会, June 2009.
• Hisashi Saito, Tomoki Kususaki, Yutaka Matsumoto, YASUYUKI MIYAMOTO, KAZUHITO FURUYA. Vertical InGaAs-MOSFET with heterostructure launcher and intrinsic channel, The 56th Spring Meeting, 2009; The Japan Society of Applied Physics and Related Societies, 1456, Mar. 2009.
• Toru Kanazawa, KAZUHITO FURUYA, YASUYUKI MIYAMOTO, Hisashi Saito, kazuya wakabayashi, Tomonori Tajima. I-V characteristics of III-V MOSFET with MOVPE regrown source region, The 56th Spring Meeting, 2009; The Japan Society of Applied Physics and Related Societies, Mar. 2009.
• YASUYUKI MIYAMOTO, Toru Kanazawa. III-V ナノデバイス, 電子情報通信学会2009年全国大会, Mar. 2009.
• Takafumi Uesawa, Masayuki Yamada, YASUYUKI MIYAMOTO, KAZUHITO FURUYA. Reduction of the base transit time in ultra-thin graded base InP/GaInAs Heterojunction Bipolar Transistor, The 56th Spring Meeting, 2009; The Japan Society of Applied Physics and Related Societies, Mar. 2009.
• Juntaro Minezaki, YASUYUKI MIYAMOTO, KAZUHITO FURUYA. Enhanced Possibility of Electron Wave Diffraction Observation with InP/GaInAs Phase-Shifter, The 56th Spring Meeting, 2009; The Japan Society of Applied Physics and Related Societies, Mar. 2009.
• Hisashi Saito, Toru Kanazawa, Yasuyuki Miyamoto, Kazuhito Furuya. Fabrication of vertical InGaAs-MOSFET with heterostructure launcher and intrinsic channel, Technical Meeting on Electron Devices, IEE Jpn., Mar. 2009.
• Takafumi Uesawa, Masayuki Yamada, YASUYUKI MIYAMOTO, KAZUHITO FURUYA. Reduction of the Base Transit Time in Ultra-thin Graded-Base InP/GaInAs Heterojunction Bipolar Transistor, Technical Report of IEICE, Electron Devices, Jan. 2009.
• Toru Kanazawa, KAZUHITO FURUYA, YASUYUKI MIYAMOTO, Hisashi Saito, kazuya wakabayashi, Tomonori Tajima. Lateral buried growth of n⁺-InGaAs source/drain region for high drive current III-V channel MOSFET, The 69th Autumn Meeting, 2008; The Japan Society of Applied Physics, Sept. 2008.
• Hisashi Saito, Ryoung-A Maeng, Yasuyuki Miyamoto, Kazuhito Furuya. Improvement of gate controllability of Hot Electron Transistor controlled by insulated gate, The 69th Autumn Meeting, 2008; The Japan Society of Applied Physics, 1262, Sept. 2008.
• Shinnosuke Takahashi, Hiroaki Yamashita, Takashi Kobayashi, Yuji Isogai, Hiroyuki Suzuki, YASUYUKI MIYAMOTO, KAZUHITO FURUYA. InP/InGaAs SHBTs with 200nm wide emitter fabricated by EB lithography, The 69th Autumn Meeting, 2008; The Japan Society of Applied Physics, Sept. 2008.
• Takafumi Uesawa, YASUYUKI MIYAMOTO, KAZUHITO FURUYA. Monte Carlo Simulation of Plasmon Scattering in Base Layer of InP/InGaAs HBTs, The 69th Autumn Meeting, 2008; The Japan Society of Applied Physics, Sept. 2008.
• So Nishimura, TUYOSHI ARAI, YASUYUKI MIYAMOTO, KAZUHITO FURUYA. 弾道電子放出顕微鏡を利用した電子波回折観測の可能性, July 2008.
• TOMOHIRO YAMADA, Takafumi Uesawa, KAZUHITO FURUYA, YASUYUKI MIYAMOTO. ゲート制御ホットエレクトロントランジスタのバリスティックモデル解析, 応用物理学会春季, 29a-D-3, Mar. 2008.
• Hisashi Saito, Maeng Ryoung-A, Yasuyuki Miyamoto, Kazuhito Furuya. Voltage gain increase of Hot Electron Transistor controlled by insulated gate, The 55th Spring Meeting, 2008; The Japan Society of Applied Physics and Related Societies, 1471, Mar. 2008.
• TOMOHIRO YAMADA, KAZUHITO FURUYA, YASUYUKI MIYAMOTO. 先端ノンドープ構造ホットエレクトロンエミッタ充電時間解析, 応用物理学会秋季, 4p-K-4, Sept. 2007.
• 高橋新之助, 三浦司, 山下浩明, 宮本恭幸, 古屋一仁. コレクタ層内にSiO2細線を埋め込んだHBTのDC特性, 応用物理学会関連連合講演会, 応用物理学会, pp. 27p-X-5, Mar. 2007.
• 山下浩明, 三浦司, 高橋新之助, 宮本恭幸, 古屋一仁. SiO2細線埋め込みHBTにおけるコレクタ容量削減のための200nm厚細線, 応用物理学会学術講演会, 応用物理学会, pp. 27a-SM-8,, Mar. 2007.
• 齋藤尚史, 諏訪輝, 長谷川貴史, 日野高宏, 大野真也, 五十嵐満彦, 宮本恭幸, 古屋一仁. 絶縁ゲートにより制御するホットエレクトロントランジスタの走行層幅微細化, 電気学会デバイス研究会, 電気学会デバイス研究会, pp. EDD-07-42, Mar. 2007.
• 日野高宏, 諏訪輝, 齋藤尚史, 宮本恭幸, 古屋一仁. 絶縁ゲートホットエレクトロントランジスタのエミッタ微細化, 応用物理学会関連連合講演会, 応用物理学会, pp. 27p-X-4, Mar. 2007.
• 諏訪輝 長谷川貴史 日野高宏 宮本恭幸 古屋　一仁. 絶縁ゲートにより制御するホットエレクトロントランジスタの作製, 電子情報通信学会電子デバイス研究会, 電子情報通信学会電子デバイス研究会, pp. ED2006-186, Dec. 2006.
• 五十嵐満彦, 山田朋宏, 町田信也, 宮本恭幸, 古屋一仁. ゲート制御ホットエレクトロントランジスタの実験構造を考慮したモンテカルロ解析, 応用物理学会学術講演会, 応用物理学会学術講演会, pp. 31p-ZB-4, Aug. 2006.
• 諏訪　輝, 長谷川貴史, 日野高宏, 宮本恭幸, 古屋一仁. 新ホットエレクトロントランジスタの室温動作にむけた新構造の提案, 応用物理学会学術講演会, 応用物理学会学術講演会, pp. 31p-ZB-3, Aug. 2006.
• 甲斐敬紹, 福山義人, 宮本恭幸, 古屋一仁. 狭メサHBTの為のノンセルフアラインメント電子ビーム露光, 応用物理学会学術講演会, 応用物理学会学術講演会, pp. 31p-ZB-2, Aug. 2006.
• 宮本恭幸, 石田昌司, 山本徹, 三浦司, 古屋一仁. MOVPEによるInP中のSiO2細線埋め込み成長とそのHBTコレクタ容量低減への応用, 電子情報通信学会電子デバイス研究会, 電子情報通信学会電子デバイス研究会, pp. ED2006-44, June 2006.
• 町田信也, 五十嵐満彦, 山田朋宏, 宮本恭幸, 古屋一仁. ゲート制御ホットエレクトロントランジスタのモンテカルロ解析, 応用物理学会学術講演会, 応用物理学会学術講演会, pp. 23a-ZE-20, Mar. 2006.
• 町田信也, 宮本恭幸, 古屋一仁. ヘテロ接合バイポーラトランジスタの最小エミッタ充電時間, 応用物理学会学術講演会, 応用物理学会学術講演会, pp. 23a-ZE-23, Mar. 2006.
• 石田昌司, 山本　徹, 三浦　司, 宮本恭幸, 古屋一仁. SiO2細線埋め込み成長によるInP系HBTのコレクタ容量低減の提案, 応用物理学会学術講演会, 応用物理学会学術講演会, pp. 23a-ZE-23, Mar. 2006.
• 鹿嶋一生, 諏訪　輝, 古屋一仁, 宮本恭幸. ゲートにより制御するホットエレクトロントランジスタにおける電流量の増大, 応用物理学会学術講演会, 応用物理学会学術講演会, pp. 23a-ZE-21, Mar. 2006.
• 鹿嶋一生, 諏訪　輝, 宮本恭幸, 古屋一仁. ゲートにより制御するホットエレクトロントランジスタにおける電流量の増大, 電子情報通信学会電子デバイス研究会, 電子情報通信学会電子デバイス研究会, pp. ED2005-196, MW2005-150, Jan. 2006.
• 町田信也, 五十嵐満彦, 山田朋宏, 宮本恭幸, 古屋一仁. ゲートにより制御するホットエレクトロントランジスタの高周波特性予測, 電子情報通信学会電子デバイス研究会, 電子情報通信学会電子デバイス研究会, pp. ED2005-197, MW2005-151, Jan. 2006.
• Y.Miyamoto, R. Nakagawa, K. Takeuchi, Y. Yamada, T. Fujisaki, M. Ishida, K. Furuya. InP ballistic hot electron transistors with 25 nm wide emitter, 24th Electronic Materials Symposium, 24th Electronic Materials Symposium, pp. E9, July 2005.
• Y. Miyamoto, M. Ishida, T. Nonaka, T. Yamamoto, K. Furuya. Tungsten buried growth by using thin flow-liner for small collector capacitance in InP HBT, 応用物理学会関係連合講演会, 応用物理学会, pp. 1a-ZM-10, Apr. 2005.
• Yasuyuki Miyamoto, Yasuhiro Watanabe. Deep submicron InP HBT, 電気学会研究会, 電気学会, pp. EDD-05-39, Mar. 2005.
• Y. Watanabe, Wei-bin Qiu, Y. MIYAMOTO, K. FURUYA. Analysis of lateral current spreading in collector of submicron HBT, 応用物理学会関係連合講演会, 応用物理学会, pp. 31p-S-1, Mar. 2005.
• T.Hattori, H.Hongo, Y.Miyamoto, KAZUHITO FURUYA, 松沼 健司, M.Watanabe, M.Asada. Seventy nm pitch CaF₂ inorganic resist pattern by electron beam exposure, Nat. Conv. Rec. of The Japan Soc. of Appl. Phys., 26a-SZW-27, 2, 565, Mar. 1996.

Other Publication

• YASUYUKI MIYAMOTO. 極微細ヘテロ接合トランジスタ, 応用物理, vol. 79, no. 11, pp. 1010-1013, Nov. 2010.

Patent

• YASUYUKI MIYAMOTO, Ryota Yamanaka, Toru Kanazawa. 半導体装置の製造方法 . Patent. Published. 国立大学法人東京工業大学, 三菱電機株式会社. 2014/08/28. 特願2014-174229. 2016/04/11. 特開2016-051722. 2016.
• YASUYUKI MIYAMOTO, Masashi Kashiwano, Toru Kanazawa. 電界効果トランジスタ. Patent. Published. 国立大学法人東京工業大学. 2013/01/09. 特願2013-001907. 2014/07/24. 特開2014-135359. 2014.
• YASUYUKI MIYAMOTO. 光電気化学装置および半導体装置の製造方法. Patent. Published. 国立大学法人東京工業大学, 三菱電機株式会社. 2012/01/23. 特願2012-011185. 2013/08/01. 特開2013-149914. 2013.
• YASUYUKI MIYAMOTO, Toru Kanazawa. 電界効果トランジスタ. Patent. Published. 国立大学法人東京工業大学. 2011/07/28. 特願2011-165385. 2013/02/07. 特開2013-030604. 2013.
• YASUYUKI MIYAMOTO. 電界効果トランジスタ. Patent. Published. 国立大学法人東京工業大学. 2010/09/13. 特願2010-204769. 2012/03/22. 特開2012-060082. 2012.
• YASUYUKI MIYAMOTO. 半導体装置の製造方法. Patent. Published. 国立大学法人東京工業大学, 日本電信電話株式会社. 2010/04/26. 特願2010-100797. 2011/11/17. 特開2011-233617. 2011.

Degree

• GaInAsP/InP Organo-Metallic Vapor Phase Epitaxy (OMVPE) for Quantum Box Lasers,  Thesis,  Doctor of Engineering,  東京工業大学,  1988/03/26,   

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